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AR# 1700

CPLD XC9500/XL - Test process of devices before shipment


Keywords : 9500 test process

What tests have been run to verify that 9500 devices are functional before they are shipped?


The test sequence involves the following steps:

1. Wafer sort #1

Logic functional tests, program/erase tests (all cells left in programmed state).

After this test, the wafer is baked at a high temperature to test for cell leakage (= charge loss). The bake is at 250 degrees C for 24 hours.

2. Wafer sort #2

Programmed cells are checked for threshold voltage changes as a result of wafer bake. After this test, bad devices (failing either wafer sort #1 or #2) are marked. All good devices are sent to be packaged.

3. Final test

Full logic functional tests and full program/erase tests. After this test, the good devices are speed-binned, marked, and shipped.

The XC9500 devices are fully tested during "final test", which is the stage when the packaged units return from packaging, and just before the devices are marked and shipped. During final test, every XC9500 device is fully tested for program/verify (both JTAG/ISP and non-ISP modes) and logic functionality (using both programmed cells and special test circuitry).

For more information on quality assurance, go to:


AR# 1700
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article