The OIF SPI 4.2 Specification indicates that you can use Maxburst1 and Maxburst2 to send the 16-byte blocks depending on the FIFO status. When HUNGRY, the PHY will expect a Maxburst2; and when STARVING, the PHY expects to receive Maxburst1. The Xilinx SPI4.2 solution does not have these two control signals.
How do we handle them?
The Xilinx SPI-4.2 solution utilizes a single FIFO for all channels, flow control is not embedded within the core. Instead, data is transferred across the SPI-4.2 bus in the order in which data is written into the Source Core. This solution allows for the most flexibility in implementing a variety of configurations, including multi-channel applications, bridge applications, etc. However, it does require that the user implement the flow control logic external to the core.
While this external logic greatly varies with the application, one common design is to implement per-channel FIFOs. For each of these FIFOs, MAXBURST1 and MAXBURST2 can be programmable thresholds within the FIFOs. Simple arbitration logic can then be designed to transfer data into the SPI-4.2 core based on the FIFO Status Channel.
An example of this can be seen on the Quad SP3 to SPI4 Bridge reference design available from
under related features.