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AR# 17067

LogiCORE Direct Digital Synthesis (DDS) v4.2 - What is the memory map information for the "A" port on the DDS Multi-Channel Core?

Description

What is the memory map information for the "A" port on the DDS Multi-Channel Core? This information is not included in the data sheet.

Solution

The memory map of port "A" is as follows: 

 

Phase Increment and Phase Offset Memory Map
Phase Increment and Phase Offset Memory Map
 

 

 

 

You can access an updated version of the data sheet containing the necessary information on the memory mapping of port "A" at: 

http://www.xilinx.com/txpatches/pub/documentation/misc/dds.pdf
 

You can patch the data sheet into CORE Generator by copying the updated PDF document into the following directory: 

 

$Xilinx\coregen\ip\Xilinx\fip2\com\Xilinx\ip\dds_v4_2\doc 

 

Example 

 

C:\Xilinx\coregen\ip\Xilinx\fip2\com\Xilinx\ip\dds_v4_2\doc)

AR# 17067
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article