The following GNU linker script illustrates one way to link an application so that it runs completely out of the PowerPC caches:

//

// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"

// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR

// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION

// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION

// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS

// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,

// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE

// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY

// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE

// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR

// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF

// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS

// FOR A PARTICULAR PURPOSE.

//

// (c) Copyright 2002 Xilinx, Inc.

// All rights reserved.

//

//---------------------------------------------------------------------------*/

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 4k;

_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 4k;

MEMORY

{

icache : ORIGIN = 0x70000000, LENGTH = 16k - 4

boot : ORIGIN = 0x70003ffc, LENGTH = 4

dcache : ORIGIN = 0x78000000, LENGTH = 16k

}

ENTRY(_boot)

STARTUP(boot.o)

GROUP(libxil.a libc.a)

SECTIONS

{

.vectors :

{

. = ALIGN(64k);

*(.vectors)

} > icache

.text :

{

*(.boot0)

*(.text)

} > icache

.data :

{

*(.data)

*(.got2)

*(.rodata)

*(.fixup)

} > dcache

/* small data area (read/write): keep together! */

.sdata :

{

*(.sdata)

} > dcache

.sbss :

{

. = ALIGN(4);

*(.sbss)

. = ALIGN(4);

} > dcache

__sbss_start = ADDR(.sbss);

__sbss_end = ADDR(.sbss) + SIZEOF(.sbss);

/* small data area 2 (read only) */

.sdata2 :

{

*(.sdata2)

} > dcache

.bss :

{

. = ALIGN(4);

*(.bss)

*(COMMON)

. = ALIGN(4);

__bss_end = .;

/* add stack and align to 16 byte boundary */

. = . + _STACK_SIZE;

. = ALIGN(16);

__stack = .;

/* add heap and align to 16 byte boundary */

_heap_start = .;

. = . + _HEAP_SIZE;

. = ALIGN(16);

_heap_end = .;

} > dcache

__bss_start = ADDR(.bss);

/* .boot must be at the end and it must be mapped to the last

address in the instruction cache. Writing to the last address

triggers the tools (GDB, svf2elf) to commit the previous write

accesses.

*/

.boot :

{

*(.boot)

} > boot

}

The following PDF file describes the flow:

http://www.xilinx.com/txpatches/pub/documentation/misc/ppc405_cache.pdf