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AR# 17185

LogiCORE Asynchronous FIFO - Verilog Behavioral Model: Reading data after the FIFO is empty produces zeroes as opposed to the last read data


When I run the Async_FIFO_v5_0 core Verilog behavioral simulation and overread the FIFO, I get the last read data on the data bus. However, when I overread the Async_FIFO_v5_1, I get 0000's on the bus.

Which behavior is correct?


In the gate-level simulation and in the actual device, the DOUT output of the FIFO will continue to show the last valid output. In the Verilog behavioral simulation, the DOUT should also remain unchanged.

The Verilog behavioral model for v5_1, v6_0, and v6_1 core is incorrect.

To work around this issue, you can perform the following:

- Ignore the DOUT bus when the FIFO is empty.

- Or Comment out line 616 of the Async_FIFO_V5_1.v model (ideal_dout=0) and recompile it (editing the behavioral model is not recommended. Xilinx strongly recommends upgrading to the latest core which is FIFO Generator).

AR# 17185
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article