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AR# 17214

3.2 EDK Processor IPs - The Memory controllers and DMA function in Processor IP do not work due to the XST issue in ISE 5.2i SP1 and ISE 5.2i SP2

Description

Keywords: DMA, OPB, PLB, IP, ATMC, Ethernet, HDLC, PCI, GEMAC, XST, EMC, DDR, SDRAM

Urgency: HOT

General Description:
The Memory controllers and DMA function in Processor IP do not work due to an XST issue in ISE 5.2i SP1 and ISE 5.2i SP2.

Solution

There is an known issue with XST in ISE 5.2i SP1 and ISE 5.2i SP2 that affects the Memory Controllers and DMA function in the following cores:
Memory Controllers
opb_emc
opb_ddr
opb_sdram
plb_emc
plb_ddr
plb_sdram

Processor IP with the DMA feature
opb_atmc
opb_ethernet
opb_hdlc
opb_pci
plb_atmc
plb_gemac

The fix is with the tactical patch. Please see (Xilinx Answer 17156).
AR# 17214
Date Created 09/03/2007
Last Updated 08/24/2009
Status Archive
Type General Article