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AR# 17254

XST - "WARNING:Xst:1610 - file.vhd line xx: Width mismatch. port has a width of y bits but assigned expression is x-bit wide."

Description

Keywords: XST, mixed, language, VHDL, Verilog, port, width, mismatch

If a Verilog module instantiates a VHDL entity in which the ports do not match the width, the following warning message occurs:

"WARNING:Xst:1610 - file.vhd line xx: Width mismatch. port has a width of y bits but assigned expression is x-bit wide."

Solution

The above warning message implies that the problem is with the VHDL file; however, the problem is actually in the instantiation in the Verilog file.

For more information on mixed language issues, please refer to (Xilinx Answer 16241).
AR# 17254
Date Created 05/13/2003
Last Updated 03/07/2006
Status Active
Type General Article