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AR# 17291

Synplify 7.2 - How do I specify the I/O standards using generics/parameters (FPGAs only)?

Description

Urgency: Standard

General Description:

The following information is from the Synplify online help:

For the Virtex family, you can use the macro libraries supplied by Synplicity to instantiate the Select I/O buffers using different I/O standards.

When you instantiate an I/O pad type in your HDL source files you can use an IOSTANDARD generic/parameter to specify the I/O standard you want. Consult the Libraries Guide for a list of all supported I/O standards.

In addition to IOSTANDARD, you can specify the following properties as generics/parameters for I/O pad types:

SLEW - output slew rate

DRIVE - output drive strength

For information on xc_padtype, please refer to (Xilinx Answer 1995).

Solution

VHDL Example

library ieee;

library virtex2;

use ieee.std_logic_1164.all;

use virtex2.components.all;

entity my_ff is

Port (d, rst, clk : in std_logic;

q : out std_logic);

end entity;

architecture my_ff_arch of my_ff is

signal clk_in, d_in, rst_in, q_in : std_logic;

begin

ibuf1 : IBUF

generic map (iostandard => "AGP")

port map (I => clk,

O => clk_in);

ibuf2 : IBUF

generic map (iostandard => "AGP")

port map (I => d,

O => d_in);

ibuf3 : IBUF

generic map (iostandard => "AGP")

port map (I => rst,

O => rst_in);

obuf1 : OBUF

generic map (iostandard => "LVTTL",

drive => 2,

slew => "fast")

port map (I => q_in,

O => q);

process (clk_in) is begin

if clk_in'event and clk_in = '1' then

if rst_in = '1' then

q_in <= '0';

else q_in <= d_in;

end if;

end if;

end process;

end architecture;

Verilog Example

`include "C:\synplicity\Synplify_72\lib\xilinx\virtex2.v"

module myff (d, rst, clk, q);

input d, rst, clk;

output q;

wire d_in, rst_in, clk_in;

reg q_in;

IBUF ibuf1 (.I(clk), .O(clk_in));

defparam ibuf1.IOSTANDARD = "AGP";

IBUF ibuf2 (.I(d), .O(d_in));

defparam ibuf2.IOSTANDARD = "AGP";

IBUF ibuf3 (.I(rst), .O(rst_in));

defparam ibuf3.IOSTANDARD = "AGP";

OBUF obuf1 (.I(q_in), .O(q));

defparam obuf1.IOSTANDARD = "LVTTL";

defparam obuf1.SLEW = "FAST";

defparam obuf1.DRIVE = 2;

always @(posedge clk_in) begin

if (rst_in)

q_in <= 1'b0;

else

q_in <= d_in;

end

endmodule

AR# 17291
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article