My top-level design contains two submodules, M0, M1, and output buffer instantiations, OBUF0. Within each submodules's source code, there is RLOC information. So, I must set keep_hierarchy when running synthesis using XST 5.2i in order to keep the RLOC information of each submodule within in its own set.
However, when I MAP the design, the following errors are reported:
"ERROR:Pack:625 - The dual data rate register "M0/reg0" failed to combine with
output buffer "obuf0" as required. Symbol "M0/reg0" is
not under the same hierarchy region as symbol "obuf0"."
This MAP error occurs because the data output of the register is not in the same hierarchy as the output buffer, but I must use keep_hierarchy when running synthesis using XST 5.2i to assign the correct RLOC information.
Use the command line option:
Or, set the "Allow Logic Optimization Across Hierarchy" in the GUI.
Set KEEP_HIERARCHY = FALSE to "M0" block in the UCF file as follows:
INST "M0" KEEP_HIERARCHY = FALSE ;