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AR# 17301

LogiCORE RapidIO - What are the bit definitions for the Logical and Physical Layer register map?


General Description: 

The Physical Layer and Logical Layer Design Guides include tables showing the register map inside each core; however, these guides do not include the individual bit definitions. Is there a document that shows what each bit is in the register map?


The configuration register map in the Physical and Logical Layer cores are the same as defined by the RapidIO Interconnect Specification. Please obtain a copy of the specification from the RapidIO Web site for information on what each bit in a particular WORD represents. The specification is available at: 


AR# 17301
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article