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AR# 17336

5.2i CORE Generator / LogiCORE XAUI v3.0 - Release Notes


Keywords: FIP4, COREGen, XAUI, XGMII, Virtex-II Pro, networking, connectivity

Urgency: Standard

General Description:
This Answer Record contains the XAUI stand-alone core F_IP4 Release Notes.


Known Issues

1. For certain CORE Generator modules, user-specified component names exceeding 24 characters in length may cause CORE Generator to hang.

To work around this issue, limit user-specified component names for CORE Generator cores to 24 or fewer characters. In addition, limit the path to the project to 12 characters. For more information, please see (Xilinx Answer 17164).

2. When implementing the XAUI v3.0 core, the following warnings are reported during PAR:

"WARNING:Timing:2667 - mdc does not clock data to mdio_out"
"WARNING:Timing:2666 - Constraint ignored: COMP "mdio_out" OFFSET = OUT 300 nS
AFTER COMP "mdc" ;"

You can safely ignore these warnings. For more information, please see (Xilinx Answer 17352).

3. BitGen errors out with the following message when implementing the XAUI v3.0 core with external XGMII:

"ERROR:DesignRules:462 - Chipcheck: Incompatible IO standards. IO standard HSTL_I
of comp xgmii_rxd<25> and IO standard LVCMOS25 of comp mdio_in are
incompatible. They cannot be in the same IO bank."

Manually lock down the pin-outs in the UCF file to work around this issue. For more information, please see (Xilinx Answer 17354).

4. The TYPE_SEL port incorrectly shows up when using the configuration/status vectors interface.

The TYPE_SEL port has no effect when the MDIO interface is not used. Consequently, this port can be left unconnected in your design. For more information, please see (Xilinx Answer 17355).

5. 'X's appear in back-annotated simulation when the MDIO interface is implemented.

To resolve this problem, add the following lines to the .ucf file and re-implement:

INST "xaui_core/BU2/u0/management_1/mdc_rising" ASYNC_REG = "TRUE";
INST "xaui_core/BU2/u0/management_1/mdio_interface_1/mdio_in_reg" ASYNC_REG = "TRUE";

For more information, please see (Xilinx Answer 17369).
AR# 17336
Date Created 05/28/2003
Last Updated 08/31/2006
Status Archive
Type General Article