We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17415

7.1i Virtex-4 RocketIO - Usage of GT11CLK in Architecture Wizard


Currently, the Architecture Wizard displays an option to choose low jitter dedicated differential clock pads as shown in Figure 1 below. This instantiates the GT11CLK module within the wrapper generated by the Architecture Wizard.  


Architecture Wizard
Architecture Wizard


Uncheck this option. To keep the clocking architecture flexible, instantiate the GT11CLK module at the top level and connect them as described in the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. To access this manual, go to the following Web page and select Doc Type, User Guides, and Virtex-4 from the list:  


This option will be removed in the next development tool release.

AR# 17415
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article