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AR# 17426

6.1i ISE - Known Issues for IP Cores (DSP, System Logic, Networking, Ethernet, System I/O, Processor)

Description


General Description:

This Answer Record contains known issues regarding the use of ISE 6.1i implementation tools for designs with IP.



Most of the networking IP mentioned here are not officially supported with ISE 6.1i. However, under brief testing, the following information has been known.

Solution


DSP and System Logic Cores

All the cores delivered with ISE 6.1i CD are compatible with ISE 6.1i implementation tools.



SPI-4.2

SPI-4.2 v5.2 and earlier are not compatible with ISE 6.1i software. Please use ISE 5.2i SP3.

SPI-4.2 v6.0 will not generate with Core Generator that is included in ISE 6.1i. Please use Core Generator that is included with ISE 5.2i software. Once the core has been generated, then it is possible to implement the design using ISE 6.1i. under following conditions:

- ISE 6.1i SP1 is needed.

- Do NOT use "-timing" switch in Map.

- For simulation: Need to have DCM clock input when resetting DCM, and Reset pulse must be 3x CLKIN periods.

- ISE 6.1i SP2 is needed to do Verilog simulation.



SPI-4.2 Lite v1.2

It is possible to implement the design using ISE 6.1i. under following conditions:

- ISE 6.1i SP1 is needed.

- For simulation: Need to have DCM clock input when resetting DCM, and Reset pulse must be 3x CLKIN periods.

- ISE 6.1i SP2 is needed to do Verilog simulation.



SPI-3 v3.1

Not supported in ISE 6.1i tool. Use SPI-3 v3.2 core.



SPI-3 v2.0.1

It is possible to implement the design using ISE 6.1, under following conditions:

- Need to edit UCF in order to target Virtex-II Pro. See (Xilinx Answer 18274).

- For simulation: Need to have DCM clock input when resetting DCM, and Reset pulse must be 3x CLKIN periods.

- ISE 6.1i SP2 is needed to do Verilog simulation.



SPI-3 v3.2

It is possible to implement the design using ISE 6.1, under following conditions:

- For simulation: Need to have DCM clock input when resetting DCM, and Reset pulse must be 3x CLKIN periods.

- ISE 6.1i SP2 is needed to do Verilog simulation.



Flexbus 4 v1.0

It is possible to implement the design using ISE 6.1i. under following conditions:

- For simulation: Need to have DCM clock input when resetting DCM, and Reset pulse must be 3x CLKIN periods.

- ISE 6.1i SP2 is needed to do Verilog simulation.



SPI-4.2 to Flexbus-4 Bridge

Not supported in ISE 6.1i tool.



1/10 Gigabit Ethernet MAC

v3.0 of these cores is not compatible with ISE 6.1i. Please use ISE 5.2i.

v4.0, which is scheduled to be available November 2003, will be compatible with ISE 6.1i.
AR# 17426
Date Created 09/03/2007
Last Updated 07/28/2010
Status Archive
Type General Article