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AR# 17494

6.1i ISE - "ERROR:16 - <TB (or TF) file name> Line 20. The module 'testbench' conflicts with a previously defined module of the same name..."

Description

Keywords: Test bench, test fixture, testbench, testfixture, conflicts, module, name, schematic, New Source, entity

Urgency: Standard

General Description:
Creating a new Test Bench or Test Fixture source to a schematic project can cause a module conflict with a previously created Test Bench or Test Fixture.

Using Project -> New Source -> VHDL Test Bench allows a user to easily create a skeleton Test Bench for an existing project source file. If the Test Bench is created for a schematic source, the Test Bench entity name will be "Testbench".

If more than one Test Bench is created for schematic sources in the project, Project Navigator issues the following Error:

"ERROR:16 - <TB File Name>.vhd Line 20. The module 'testbench' conflicts with a previously defined module of the same name.
The definition must be resolved before processes will be available for the source."

Likewise, if Project -> New Source -> Verilog Test Fixture process is used to add more than one Test Fixture for schematic sources, Project Navigator issues the following Error:

"ERROR:16 - <TF File Name>.v Line 5. The module 'testfixture' conflicts with a previously defined module of the same name.
The definition must be resolved before processes will be available for the source."

Solution

Although this Error is issued, the Test Bench or Test Fixture will be successfully created and opened in the ISE Text Editor (or user-defined editor).

Change the entity or module name of the Test Bench or Test Fixture file to a unique name. This will eliminate the error and allow the files to be displayed correctly in the hierarchy of the Sources window.
AR# 17494
Date Created 06/20/2003
Last Updated 02/07/2006
Status Archive
Type General Article