10.1 Floorplan Editor/PACE - Incorrect nets are displayed for a hierarchical schematic design
Description
Keywords: net, schematic, design
My design is a schematic created with ECS, inside Project Navigator. I run "Assign Package Pins" from the Project Navigator GUI, and it displays the PACE GUI. In the "Design Browser" window, when I click on I/O Pins, the wrong pin names display, and if I select-drag-release any of them on the "Device Architecture" window and save, the ".ucf" file created causes NGDBuild to fail as follows:
"Annotating constraints to design from file "uuu.ucf" ...
ERROR:NgdBuild:755 - Line 6 in 'uuu.ucf': Could not find net(s) 'A0' in the
design. To suppress this error specify the correct net name or remove the
constraint. The 'Ignore I\O constraints on Invalid Object Names' property
can also be set ( -aul switch for command line users)."
Solution
In this case, the "top_sc.vhd" file has the data for a lower-level entity written first. These are the ports that are displayed in PACE, because it assumes that the top-level entity is found first. Modify the "top_sc.vhd" file so that the top level is at the top of the file, or create a new "top.vhd" file with only the top-level entity.This should be fixed in the next major release of the design tools.