UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17508

6.1i Clocking Wizard/ECS - A schematic symbol from an XAW or VHDL/Verilog instantiation template creates an incorrect STATUS bus width

Description

General Description: 

When I generate a schematic symbol from an XAW file with the Clocking Wizard, a symbol is created with an 8-bit STATUS bus. The STATUS bus should be 3 bits or (2:0). As a result, an error occurs during synthesis.

Solution

This issue is scheduled to be fixed in the ISE 7.1i software release.

AR# 17508
Date Created 09/03/2007
Last Updated 05/08/2014
Status Archive
Type General Article