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AR# 17604

6.1i:Timing Analyzer - How do I create a constraint for clock-forwarding that goes FROM my input clock pad THRU the FF clock pin TO my DDR output clock pad?

Description

General Description:

A DDR output for clock forwarding is being fed by my input clock. I would like to see the total delay of this path (FROM pad TO pad). How do I create a constraint that shows this path?

Solution

Starting in 6.1.01i, our tools allowed the clock pin of a FF to be used as a THRU point on a FROM:THRU:TO constraint. In order to do this, there are a couple of things that need to be done.

1. Create a THRU point using the TPTHRU attribute that contains the clock pins of the DDR Flip-Flops. The easiest way to get these names is from the Xilinx Constraints Editor. Once you have the instance names of the FFs, you can grab the clock pins by doing the following:

Example instance name of DDR FF is "CLK40P92_FWD/FDDRCPE1"

Constraints to get the clock pins of this DDR FF into at THRU group:

PIN "CLK40P92_FWD/FDDRCPE1.C0" TPTHRU = "thru_grp";

PIN "CLK40P92_FWD/FDDRCPE1.C1" TPTHRU = "thru_grp";

2. Create a FROM and TO group that contains the pads you wish to start and end at:

INST "clk_52" TNM = "from_grp";

INST "clk_40p92" TNM = "to_grp";

3. Create a FROM:THRU:TO constraint for this path:

TIMESPEC "TS_01" = FROM "from_grp" THRU "thru_grp" TO "to_grp" 20 ns;

The value specified here (20 ns) is not really important. The value should be large enough that the tools do not error out on it, but it will not actually affect any Place and Route results.

The constraints given in steps 1 through 3 should be added to the UCF file. A completed UCF for this constraint would look like the following:

#********************************************

INST "clk_52" TNM = "from_grp";

INST "clk_40p92" TNM = "to_grp";

PIN "CLK40P92_FWD/FDDRCPE1.C0" TPTHRU = "thru_grp";

PIN "CLK40P92_FWD/FDDRCPE1.C1" TPTHRU = "thru_grp";

TIMESPEC "TS_01" = FROM "from_grp" THRU "thru_grp" TO "to_grp" 20 ns;

#*********************************************

Example path from above constraints: (NOTE: Only 1 path of the 2 existing is shown below)

================================================================================

Timing constraint: TS_01 = MAXDELAY FROM TIMEGRP "from_grp" THRU TIMEGRP "thru_grp" TO TIMEGRP

"to_grp" 20 nS ;

2 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)

Maximum delay is 8.125ns.

--------------------------------------------------------------------------------

Slack: 11.875ns (requirement - data path)

Source: clk_52 (PAD)

Destination: clk_40p92 (PAD)

Requirement: 20.000ns

Data Path Delay: 8.125ns (Levels of Logic = 2)

Data Path: clk_52 to clk_40p92

Delay type Delay(ns) Physical Resource

Logical Resource(s)

---------------------------- -------------------

Tiopi 0.722 clk_52

clk_52

C_clk_52

net (fanout=8) 0.182 N_clk_52

Tgi0o 0.589 BGM40p92

BGM40p92

net (fanout=2) 1.926 clk_40p92_t

Tiockp 4.706 clk_40p92

CLK40P92_FWD/FDDRCPE1/FF0

CLK40P92_FWD/OBUF1

clk_40p92

---------------------------- ---------------------------

Total 8.125ns (6.017ns logic, 2.108ns route)

(74.1% logic, 25.9% route)

This problem has been fixed in the latest 6.1i Service Pack available at:

http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 6.1i Service Pack 1.

An OFFSET/OUT constraint can be used in this instance; the OFFSET constraint shows both the data and clock paths. These can be added together to generate the same results that will be created using Resolution 2.

For more information on OFFSET constraints, please see the Constraints Guide in the appropriate software manual version at:

http://support.xilinx.com/support/software_manuals.htm

This problem has been fixed in the latest 6.1i Service Pack available at:

http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 6.1i Service Pack 1.

AR# 17604
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article