We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17651

iMPACT - JTAG programming fails when the DONE pins are tied together


When I use the iMPACT toolto configure a JTAG chain containing FPGAs with the DONE pins tied together, the parts do notcomplete configuration. The I/Os are tri-stated and sending an additional JTAG clock does not resolve this issue. In the Status Register, GHIGH is '1', but the other startup signals are '0'.

How do I resolve this issue?


When oneFPGA is programmed and the other is not, the unconfigured device drives the DONE pins Low. As DONE is released and not driven High, this prevents the configuration from completing.

Solution 1

Assign configuration files to all devices in the chain and program with all devices in the JTAG chain selected.

Solution 2

Manually generate the SVF file that performs JSTART, sends in an additional TCK, and includes a bypass instruction. This takes the device out of the startup sequence.

Example for one Virtex-II device in the chain

// Loading device with a 'jstart' instruction.

SIR 6 TDI (0c) TDO (00) ;

//Loading device with 'bypass' instruction.

SIR 6 TDI (3f) ;

Solution 3

Set GTS and GWE to be released during the same cycle as DONE.

Solution 4

Ensure that you have generated a ".msk" file with each bit file. Program all devices in the JTAG chain. After programming, issue each device with a Verify operation. This forces the device to start up.

NOTE: If the device is a Spartan-6 FPGA, there is an additional concern in this situation. If a Spartan-6 device has a watchdog timeout errordue to DONE being held Low,then it will drive INIT and DONE Low. This can prevent JTAG access and configuration on other devices.

The safepractice is to havea hardwarejumper to separate the DONE pin and the INIT_B pin duringJTAG programming, so each device can be programmed separately.

AR# 17651
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex
  • Virtex-4 FX
  • Virtex-4 LX
  • More
  • Virtex-4 SX
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Virtex-II
  • Virtex-II Pro
  • Spartan-3
  • Spartan-3A
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-II
  • Less
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • Less