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AR# 17663

LogiCORE SPI-4.2 (POS-PHY L4) v6.0/v6.0.1 - Release Notes (PL4 Customers Only)


This Answer Record contains the Release Notes for SPI-4.2, also known as POS-PHY Level 4 (PL4) version 6.0 and v6.0.1, and includes the following: 


- Software Requirements 

- What's New in SPI-4.2 v6.0 

- Supported Device/Package Information 

- Known Issues 

- What's New in SPI-4.2 v6.0.1 


NOTE: This version of the SPI-4.2 (v6.0) is now obsolete. Please use the latest version, available from Software Update page: 



Software Requirements 

The Xilinx CORE Generator 5.2i (included with the ISE 5.2i software) is required to use PL4 v6.0. Additionally, the following service packs and IP updates must be installed with ISE 5.2i prior to installing the "pl4_v6_0.zip" or "pl4_v6_0.tar.gz." 


The recommended order of installation is as follows: 

1. ISE 5.2i CD 

2. ISE 5.2i Service Pack 3 

3. ISE 5.2i IP Update 2 (also known as F_IP2) 

4. "pl4_v6_0.zip" or "pl4_v6_0.tar.gz" (available only to PL4 customers) 


Software Service Packs are available at: 


IP Update 2 is available at: 


"PL4-v6_0.zip" is available (PL4 customers only) at: 


What's New in PL4 v6.0 


General Features 

- Selectable 64- or 128-bit User Interface 

- Option to 3-state SPI-4.2 outputs 

- Additional reset signals enabling the Sink or Source FIFO to be reset without resetting the entire core 

- Virtex-II Pro files delivered through CORE Generator 

- Expanded Device/Package Support 


Source Core 

- Option to transmit only complete data burst 

- Support for both master and slave clocking 

- Option to use Addressable Mode or Transparent Mode FIFO Status Information 

- Diagnostic tool enabling forced insertion of DIP4 errors 


Sink Core 

- Enhanced Dynamic Phase Alignment (DPA) to support wider frequency up to 944 Mbps 

- New Output Signal "DCMLost_RDClk" to indicate Sink core is not receiving valid RDClk 

- Improved error handling: Sink FIFO Burst Error and Sink FIFO Payload DIP4 Error 


Supported Device and Package Information 


PL4 v6.0 Virtex-II Device Package Table 


PL4 v6.0 Virtex-II Pro Device Package Table 


Known Issues 

Please see (Xilinx Answer 12420) for a list of PL4 Known Issues. 


What's New in SPI-4.2 v6.0.1 

SPI-4.2 v6.0.1 Core contains minor upgrade to v6.0. Most of the features and known issues for v6.0 cores still apply. However, following issues have been updated: 


1. SPI-4.2 v6.0 GUI points to the v5.2 data sheet when I click "DATA SHEET". v6.0.1 GUI now points to the v6.0.1 (the latest) data sheet. 

2. Dynamic Phase Alignment Sink core might not go in-frame due to a missing timing constraint. See (Xilinx Answer 18167). This issue has been fixed in SPI-4.2 v6.0.1. 

3. Virtex-II Pro Sink core: The "Use inverted CLK0 to generate CLK180" option has been removed from the Sink core GUI. If this feature is still needed, please open a WebCase and escalate the issue to an SPI-4.2 expert. 


AR# 17663
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article