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AR# 17686

LogiCORE SPI-4.2 (POS-PHY L4) v6.1 - Simulation reports a setup and hold violation and unknown "x" is shown on SPI-4.2 signals during simulation


General Description: 

When I simulate an SPIN-4.2 core, an unknown state or "x" is reported on the signals along with setup and hold time violations. The signals known to have this issue are: 




(There may be other undiscovered signals, as well) 


The simulator reports error such as: 


"Timing Violation Error : Setup time"  

"815 violated on X_RAMB16_S9_S9 instance : top.pl4_snk_top0.\pl4_snk_core0/c1_c1.pl4_snk_cal0/mem_mem.CalRAM/BlockRam .display_all_a_b on CLKA port at simulation time 2455000 ns with respect to CLKB port at simulation time 2455815. Expected setup time is 1000."


The timing violation is due to SPI-4.2 internal registers crossing the asynchronous clock domains. The unknown state appearing on the output signals will not affect the functionality of the core. However, in simulation, the unknown states might propagate through the design and can cause undesired effects. 


If unknown states are reported during simulation, Xilinx recommends using the "-xon false" switch for NGD2VHDL for VHDL simulation and the simulator switch on Verilog simulation to prevent the unknown state from propagating. 


To regenerate VHDL simulation files: 

prompt> ngdbuild pl4_src_top.edn 

prompt> netgen -ofmt VHDL -sim -XON false pl4_src_top.ngd pl4_src_top.vhd 


For Verilog, use the simulator-specific switches to turn off "x"or unknown state propagation. In this case, it would not be necessary to re-generate the simulation model.

AR# 17686
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article