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AR# 17687

LogiCORE SPI-4.2 (POS-PHY L4) v6.0 - Speed file patches needed to avoid timing violations on SPI-4.2 v6.0 cores


General Description: 

This Answer Record explains why speed file patches are needed for SPI-4.2 v6.0 cores.


For Virtex-II devices: 

If you are performing gate-level (post-NGD, or post-timing) simulation using VHDL simulator and you are running the SysClk faster than 300 MHz, you might see "x" or unknown state appearing on the TDClk output due to pulse-swallowing. 


For Virtex-II Pro devices: 

If you are using an SPI-4.2 core and are using a -6 or -7 Virtex-II Pro device, you may have a problem meeting SPI-4.2 timing constraints. 


For the above two issues, please download and install the appropriate speed files: 

Virtex-II: http://www.xilinx.com/txpatches/pub/swhelp/speed_files/2v1-116.zip  For more information, please see (Xilinx Answer 17716)  

Virtex-II Pro: http://www.xilinx.com/txpatches/pub/swhelp/speed_files/2vp1-81.zip  For more information, please see (Xilinx Answer 17719)

AR# 17687
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article