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AR# 17709

9.1i PrimeTime/netgen - Which Xilinx constraints are not supported by PrimeTime flow?

Description

Which Xilinx constraints are not supported by PrimeTime flow?

Solution

The following conventions are not supported by PCF2SDC: 

 

- Offset translations for DCM (for a multi-DCM clock design) 

- TIMEGRPs with EXCEPT (TIMEGRP <id> = TIMEGRP <id>... EXCEPT TIMEGRP <id>;)  

- MAXDELAY between clock domains  

- Non-PIN constraints  

- TIMEGRPs with rising/falling group qualifiers  

- NET/INSTANCE TIGs with/without Timespec (set_false_path -from -to all elements connected to net)  

- DCM introduced Jitter/Phase-Shift-Errors 

- MAXDELAY PAD-2-PAD with DCM in the path  

- Global Offsets with HIGH/LOW qualifier (Gm)

AR# 17709
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article