The following error occurs when I run place and route (PAR) on a design with an SPI-4.2i core targeting an XC2VP70-FF1704 device.
"ERROR:Place:44 - The global clocks pl4_src_top0/pl4_src_clk0/DCM_highspeed.tdclk180_bufg0 (BUFGMUX5S) and pl4_snk_top0/pl4_snk_clk0/LowFreq.StaticAlign_StaticAlign.snkclk_bufg0 (BUFGMUX5P) are locked into a primary/secondary site pair. It is impossible to route all of the clock loads for both of these clocks using the global clock routing resource. Only one of primary/secondary pair clocks have access to any one quadrant via global (high drive/low delay/low skew) routing resources. If these two clocks drive clock inputs in the same quadrant the nets will not be routable using the global clock routing resources."
This results in the design failing timing.
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