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AR# 17758

6.3i/6.2i/6.1i XST - "ERROR:DesignRules:599 - Blockcheck: Both the IFF1 and IFF2 Flip-Flops of comp d<7> must be programmed the same, either FF or LATCH"


Keywords: MAP, Virtex-II, Spartan-3, Spartan-III

When I use XST to make a latch and a flip-flop on the same input port, the following error occurs during MAP:

"ERROR:DesignRules:599 - Blockcheck: Both the IFF1 and IFF2 Flip-Flops of comp
d<7> must be programmed the same, either FF or LATCH.
ERROR:Map:46 - Errors in physical DRC."

MAP is trying to pack a flip-flop and a latch into the same input IOB. The following Verilog and VHDL code causes the problem:

module latchff(d,clk,ge,q1,q2);
input [7:0] d;
input clk;
input ge;
output [7:0] q1;
output [7:0] q2;

reg [7:0] q1, q2;

always @(posedge clk) //in==>FF
q1 <= d;

always @(d or ge) //in==>LATCH
if (ge) q2 <= d;


library IEEE;

entity latch_ff is
Port ( d : in std_logic_vector (7 downto 0);
clk : in std_logic;
ge : in std_logic;
q1 : out std_logic_vector (7 downto 0);
q2 : out std_logic_vector (7 downto 0));
end latch_ff;

architecture Behavioral of latch_ff is


process (clk) is begin

if clk'event and clk = '1' then
q1 <= d; --in==>FF
end if;
end process;

process (d, ge) is begin
if (ge = '1') then
q2 <= d; --in==>Latch
end if;
end process;

end Behavioral;


This issue has been fixed in ISE 7.1i

To work around this issue, turn off "Pack I/O register into IOB" and turn off the MAP switch "PACK I/O registers and Latches into IOB" as follows:

1. With your ISE project open, right-click the "Synthesize" process.
2. Select Properties...".
3. Select the "Xilinx Specific Options" tab.
4. Set "Pack I/O Registers into IOBs' to "No".
5. Press the "OK" button.
6. Right-click the "Implement Design" process.
7. Select "Properties...".
8. Select the "Map Properties" tab.
9. Set the "Pack I/O Register/Latches into IOBs" to "Off".
10. Press "OK".
AR# 17758
Date Created 09/03/2007
Last Updated 01/06/2009
Status Archive
Type General Article