UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17773

3.1 SP1 System Generator for DSP - Release Notes and Known Issues List for Service Pack 1

Description

General Description:

What are the known issues for System Generator v3.1 SP1?

Solution

Support Software Issues

1. MATLAB R12 and R12.1 are not supported by System Generator for DSP v3.1 SP1. (Only MATLAB R13 is supported.) Please see (Xilinx Answer 16827).

2. The recommended minimum install is 5.2i Service Pack 1. Please see (Xilinx Answer 17966).

3. Why do I get "libhsimengine.dll" and "libPortability.dll" when trying to open the Xilinx Block Set in MATLAB R13? Please see (Xilinx Answer 16928).

4. Why does an extra cycle of latency occur in my design when I use Synplify 7.2.2? Please see (Xilinx Answer 16934).

Xilinx Block Set Issues

1. The CIC filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. To work around this problem, do not use the full dynamic range of your input. Please see (Xilinx Answer 12480).

2. Decimation filters with a down sampling of "2" and symmetry in the impulse response fail in core generation. Please see (Xilinx Answer 15685).

3. Updating a SysGen 2.1 model to SysGen 3.1 model causes errors. Please see (Xilinx Answer 16828).

4. PicoBlaze fails to compile when using the Leonardo synthesis tool. Please see (Xilinx Answer 16923).

5. PicoBlaze compiler script fails when using long module names. Please see (Xilinx Answer 16924).

6. The DDS fails to generate if Phase Dithering is selected and the Phase Angle is greater than the Phase Accumulator. Please see (Xilinx Answer 16927).

7. MAP reports errors when XST is used to synthesize a design containing the DDS core. Please see (Xilinx Answer 16935).

8. ROM Blocks for Spartan-3 fail to generate properly. Please see (Xilinx Answer 16926).

9. DA FIR core is larger than expected. Please see (Xilinx Answer 18214).

10. FFT not generated for Virtex-2 Family when using ISE 6.1i. Please see (Xilinx Answer 18227).

General Issues

1. The following error occurs during generation: "Undefined function or variable." Please see (Xilinx Answer 15190).

2. 3.1 SP1 System Generator for DSP - Release Notes / README. Please see (Xilinx Answer 18122).

AR# 17773
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article