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AR# 17800

LogiCORE SPI-4.2 (POS-PHY L4) v6.0 - Migrating from v5.2 to v6.0 (Migration Guide)

Description

General Description: 

This Answer Record describes how to migrate from v5.2 to v6.0 of the SPI-4.2 Core. It also describes the signal changes made to the Core. While every attempt was made to keep constraints and input and output signals as consistent as possible between versions, certain modifications are required to upgrade from v5.2 to v6.0. The following sections are included in this Answer Record: 

 

- Core Signal Changes 

- Wrapper File Changes 

- NCF File Changes 

- UCF File Changes 

- UCF Migration Steps

Solution

Core Signal Changes 

 

NOTE: The following signals were added/removed from the v6.0 Core. 

 

SrcSelFullRate(Input) - existed in v5.2, removed in v6.0 

This input signal was used to selectively operate the Core at either full rate or half rate. It was removed because it introduced a BUFGMUX into the design, which consumed a BUFG adjacent to where the BUFGMUX was placed. To run the Core at half or quarter rate, use the v6.0 Slave Core and implement half or quarter rate clocking. A design example on Slave clocking is available on the SPI-4.2 Lounge. 

 

PhaseAlignEn (Static Configuration) - existed in v5.2, removed from v6.0 

This Static Configuration signal was used to enable the Automatic Static Alignment feature in the Sink core. However, this feature is not supported in V6.0. The data-clock alignment on the sink SPI-4.2 bus must be done either by using Dynamic Alignment configuration or by using Fixed Static Alignment configuration, which requires choosing the appropriate phase shift value for the DCM and setting it in the UCF. See (Xilinx Answer 16112).  

 

PhaseAlignErr(Output) - existed in v5.2, removed from v6.0 

This output signal was used to indicate the status of Automatic Static Alignment. This is no longer needed because Automatic Static Alignment is not supported in v6.0. Either remove it from your design, or leave it unconnected. 

 

SnkFFPayloadDIP4 (Output) - new in v6.0 

Please see the data sheet for more information. If not needed, leave unconnected. 

 

SnkFFBurstErr (Output) - new in v6.0 

Please see the data sheet for more information. If not needed, leave unconnected. 

 

SnkFiFoReset_n (Input) - new in v6.0 

Please see the data sheet for more information. If not needed, tie it to "1." 

 

SrcFiFoReset_n (Input) - new in v6.0 

Please see the data sheet for more information. If not needed, tie it to "1." 

 

SrcTriStateEn (Input) - new in v6.0 

Please see the data sheet for more information. If not needed, tie it to "0." 

 

DCMLost_RDClk (output) - new in v6.0 

Output signal to indicate that RDClk has stopped toggling. Please see the data sheet for more information. In not needed, leave unconnected. 

 

SrcBurstMode (Static Configuration) - new in v6.0 

If SrcBurstMode is set to "0", the Source core transmits data in the FIFO whenever there is a complete credit of data or when there is an end of packet flag (SrcFFEOP.) When SrcBurstMode is set to "1", the Source core only transmits data that is terminated by an EOP or when there is data in the FIFO equal to the maximum burst length defined by the static configuration signal SrcBurstLen. Please see the data sheet for more information. 

 

Wrapper File Changes 

The v6.0 wrapper file replaces the v5.2 wrapper file, or manually add/delete the signal changes mentioned above. 

 

NCF File Changes 

The v6.0 NCF files replace the v5.2 NCF files. 

 

UCF File Changes 

The UCF file must be updated via either Option A or Option B below:  

 

Option A 

Replace all SPI-4.2 constraints in the UCF file with the SPI-4.2 constraints provided in the v6.0 release (use the v6.0 UCF files instead of the v5.2 UCF files). 

 

Option B 

Follow the instructions below ("UCF Migration Steps") to migrate the existing PL4 UCF constraints so they are compatible with v6.0. Note that the "#" character can be substituted for numbers and "<>" are used as fillers following phrases. 

 

UCF Migration Steps 

 

Sink Constraints 

 

Clocking 

The hierarchical path of the sink clock module is changed as shown in the following examples: 

 

Static Alignment Cores 

INST "pl4_snk_top0/pl4_snk_clk0/StaticAlign_StaticAlign.<>"... 

 

is changed to: 

 

INST "pl4_snk_top0/pl4_snk_clk0/LowFreq.StaticAlign_StaticAlign.<>"... 

 

Dynamic Alignment Cores 

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlign_DynamicAlign.<>"... 

 

is changed to: 

 

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.<>"... 

 

Area Constraints 

Use v6.0 area group range (AG_pl4_snk). 

 

Block RAM Placements 

The hierarchical path of the block RAMs is changed as shown in the following examples: 

 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_sfifo0/pl4_sfifo_top0/generic_fifo_ram0/BlockRAMgen_BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.#.BlockRAM36" LOC = "RAMB16_X#Y#" 

 

is changed to: 

 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_afifo0/pl4_generic_fifo0/generic_fifo_ram0/BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.#.BlockRAM36" LOC = "RAMB16_X#Y#" 

 

Add one additional block RAM (place on top or bottom of other block RAMs). 

 

NOTE: You might get a map error if you use a BRAM that is already being used. 

 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_afifo0/pl4_generic_fifo0/generic_fifo_ram0/BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.4.BlockRAM36" LOC = "RAMB16_X#Y#" 

 

The hierarchical path of the calendar block RAMs is also changed: 

 

INST "pl4_snk_top0/pl4_snk_core0/c1_c1.pl4_snk_cal0/mem_mem.CalRAM/BlockRam"... 

 

is changed to:  

 

INST "pl4_snk_top0/pl4_snk_core0/c1.pl4_snk_cal0/mem.CalRAM/BlockRam" 

 

Add two additional block RAMs (use the RAMB16 locations used in v6.0 UCF): 

 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_u10/size_bram_0/size_ram1" LOC = "RAMB16_X#Y#"; 

INST "pl4_snk_top0/pl4_snk_core0/pl4_snk_u10/size_bram_0/size_ram0" LOC = "RAMB16_X#Y#"; 

 

I/O RPMs: the hierarchical path of the sink I/O is changed. Also, use new RLOC_ORIGIN value for I/O placement: 

 

INST "pl4_snk_top0/pl4_snk_io0/SnkTDat_gen.SnkTDat_gen.3.SnkTDat_Mux" RLOC_ORIGIN=X#Y# 

 

is changed to: 

 

INST "pl4_snk_top0/pl4_snk_io0/SnkTDat_gen.3.SnkTDat_Mux" RLOC_ORIGIN=X#Y# 

 

Source Constraints 

 

Clocking 

The hierarchical path of the source clock module is changed as shown in the following examples: 

 

INST "pl4_src_top0/pl4_src_clk0/DCMUsed_DCMUsed.<>"... 

 

is changed to: 

 

INST "pl4_src_top0/pl4_src_clk0/DCM_highspeed.<>"... 

 

When the TDClk DCM bypass feature is used: 

INST "pl4_src_top0/pl4_src_clk0/DCMBypassed_DCMBypassed.<>"... 

 

is changed to: 

 

INST "pl4_src_top0/pl4_src_clk0/DCMBypassed.<>"... 

 

TSClk DCM : 

INST "pl4_src_top0/pl4_src_clk0/tsclk_<>"... 

 

is changed to: 

 

INST "pl4_src_top0/pl4_src_clk0/TSClkFullRate.tsclk_<>"... 

 

Area Constraints 

Use v6.0 area group range (AG_pl4_src). 

 

Block RAM Placements: the hierarchical path of the block RAMs is changed as shown in the following example: 

 

INST "pl4_src_top0/pl4_src_core0/pl4_src_fifo0/PL4_FIFO/generic_fifo_ram0/BlockRAMgen 

_BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.#.BlockRAM36" LOC = "RAMB16_X#Y#" 

 

is changed to: 

 

INST "pl4_src_top0/pl4_src_core0/pl4_src_fifo0/PL4_Source_FIFO/pl4_async_burst_fifo_ram 

0/BlockRAMgen.RamGen36_RamGen36.GenRAM36.GenRAM36.#.BlockRAM36" LOC = "RAMB16_X#Y#" 

 

The hierarchical path of the calendar block RAMs is changed as shown in the following example: 

 

INST "pl4_src_top0/pl4_src_core0/c1_c1.pl4_src_cal0/crtram_crtram.cram/BlockRam"... 

 

is changed to : 

 

INST "pl4_src_top0/c1.pl4_src_cal0/crtram.cram/BlockRam"... 

 

I/O RPMs: the hierarchical path of the source I/O is changed as shown in the following example. Also, use new RLOC_ORIGIN value defined in v6.0 UCF for I/O placement. 

 

INST "pl4_src_top0/pl4_src_io0/src_rdy.src_rdy.2.rdy_hi_rdy_hi.src_rdy_hi" RLOC_ORIGIN=X#Y# 

 

is changed to: 

 

INST "pl4_src_top0/pl4_src_io0/src_rdy.2.rdy_hi_rdy_hi.src_rdy_hi" RLOC_ORIGIN=X#Y#

AR# 17800
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article