The power budget for my design is exceeded. How do I reduce (dynamic) power in a design?
One component of dynamic power is the result of switching activity on nets. Therefore, the goal is to eliminate any unnecessary switching in the design. The following are some ideas:
1. Turn off clocks when they are not in use by using BUFGCE (Virtex-II/Pro/-4 and Spartan-3/-3E).
2. Have block RAMs operate in "No read on write" mode. This reduces toggling of the output of the block RAM.
3. Use clock enables to reduce switching activity on the output of FFs.
Dynamic power is also dependant upon capacitance; net length affects capacitance.
4. Partition clocks into quadrants and reduce the number of quadrants to which the clock is routed.
5. Reduce the total number of columns to which a clock is routed.
6. Reduce the total length of heavy loaded signals.
(The previous three points can be achieved by using Floorplanner/PACE.)
NOTE: The impact of any of the above changes is design-dependant; each action should be carefully assessed.