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AR# 17822

5.2i ISE - "View VHDL Instantiation Template" and "Create Schematic Symbol" create incorrect result if using exponents in the declaration

Description

Keywords: XST, VHDL, instantiation, template, schematic, symbol, exponent, declaration

Urgency: Standard

General Description: "View VHDL Instantiation Template" and "Create Schematic Symbol" create incorrect result if using exponents in the declaration.
Example:
Line in declaration of component: "my_sig : in std_logic_vector(((2**3) -1) downto 0);"
Line in port map of created template: "my_sig: IN std_logic_vector(66 downto 0);"

Solution

The result is not correct. Please modify the template with the correct value, in the example above:
"my-sig : IN std_logic_vector(((2**3) -1) downto 0);"

This problem has been corrected in the ISE 6.1i software release.
AR# 17822
Date Created 08/19/2003
Last Updated 02/07/2006
Status Archive
Type General Article