Keyword: fatal, error, timing, clock, arrival, time
Starting initial Timing Analysis. REAL time: 5 secs
For DDR , putting TIG on inverted clock reports :-
FATAL_ERROR:Timing:bastwoffsetpref.c:575:18.104.22.168 - Clock arrival time not
found! Process will terminate. To resolve this error, please consult the
Answers Database and other online resources at http://support.xilinx.com. If
you need further assistance, please open a Webcase by clicking on the
"WebCase" link at http://support.xilinx.com
This is a bug in the software. There is a simple workaround. The pcf file supplied in the bug cases directory uses a TIG on the clock pin of a flip flop in the IOB. This is what causes the fatal message. Instead of using a TIG on the clk pin the user can change the offset out constraint. Here the User is trying to constraint the clock to out path for one of two flip flops used in the IOB. To do this they have added the IOB and the CLK to an offset out constaint and tigged the comp pin that drives one of the flip flops clock. The work around is to place the flip flop they want to constrain into a time group and apply an offset out to the time group and the CLK. I have supplied a working .pcf file called mapped2.pcf into the bug cases directory.
*** NOTES 08/11/2003 10:30:16 AM mbixler
Since there is an easy work around, constrain the bel of interest, this bug should be marked not scheduled. Timing does not specifically support TIGing a clk pin and a fix would take some time. Unless Marketing or Apps can justify this feature then Timing will recomend using a different constraint method such as the work around.
*** NOTES 08/11/2003 09:43:18 AM shiv
The problem with work around (PCF) is that it may not be possibile to do same through UCF
because grouping DDR instance in UCF results in group both BEL's of DDR instance in pcf.