Sending invalid DIP2 to the SPI4.2 core does not assert SrcDIP2Err. Why is this?
This behavior is seen in both simulation and in the hardware.
Immediately after the Xilinx SPI 4.2 source core goes out of frame (SrcOof = '1'), the core will resync itself to the first "11" to non "11" transition (on the TStat bus ) as a start of a status sequence.
Hence, the last DIP2 before this transition will be ignored and SrcDIP2Err will not be asserted for this DIP2.