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AR# 17952

Timing Simulation, NETGEN - How can I re-use (reuse) a testbench with generics in post-Place and Route (Timing) simulation?

Description

I have a testbench that I wrote for functional simulation that have generics in them. When I try to reuse this testbench in my Timing simulation, the simulator errors out about the entity in testbench not matching the gate-level net list.

Is there a way to work around this?

Solution

There is a way to work around this without having to write a new testbench for the post-Place and Route simulation netlist.

Using the -a switch with NetGen will generate an architecture only back-annotated HDL file.

In doing so, the entity of the RTL definition that contains the generic can be re-used and, as long as the top-level ports are defined as std_logic_vector, it should be able to bind the entity to the gate-level netlist.

Example netgen command:

netgen -sim -a <infile> [<outfile>]

AR# 17952
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article