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AR# 18011

6.1i ISE Install - Service Pack 3 Release Notes/README


Keywords: Service Pack, 1, 2, 3, Solaris, UNIX, PC, Linux, software, update, 6.1i, SP1, SP2

This README Answer Record contains the Release Notes for 6.1i Service Pack 3. The Release Notes include installation instructions and a list of the issues that are fixed by this and previous Service Packs for the 6.1i release.



A successful installation of Xilinx ISE 6.1i Service Pack 3 updates your software version number to 6.1i

NOTE 1: The destination directory specified during the set-up operation must contain an existing Xilinx ISE 6.1i installation. Only existing files will be updated. Any new device support not previously installed should first be installed from the Xilinx ISE 6.1i CD before adding Service Pack 3.

NOTE 2: The Xilinx ISE 6.1i environment variable should be set before commencing the installation of Service Pack 3.

Installation instructions for PC users:
1. Download 6_1_03i_pc.exe from:
2. Run "6_1_03i_pc.exe".


1. Establish a working Internet connection using Internet Explorer.
2. Use the Webupdate program by one of the following methods:
a. Run "Start -> Programs -> ISE6 -> Accessories -> Webupdate".
b. Run "Software Updates..." found under the Help menu in Project Navigator.

Installation instructions for Solaris users:
1. Download 6_1_03i_sol.tar.gz from:
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 6_1_03i_sol.tar.gz
tar xvf 6_1_03i_sol.tar

3. Run "6_1_03i_sol/setup".

Installation instructions for Linux users:
1. Download 6_1_03i_lin.tar.gz from:
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 6_1_03i_lin.tar.gz
tar xvf 6_1_03i_lin.tar

3. Run "6_1_03i_lin/setup".


Issues Fixed by 6.1i Service Packs:

Architecture Wizard

(SP2) 6.1i Virtex-II/Pro DCM - The CLKFX jitter calculator result differs between the Architecture Clocking Wizard and the Web. (Xilinx Answer 17819)
(SP2) 6.1i Architecture Wizard, RocketIO Wizard - The receiver-only module does not function; TXUSRCLK ports are not brought out. (Xilinx Answer 17929)
(SP1) 6.1i Clocking Wizard - The Board De-skew flow does not restrict a 2X clock in the low-frequency mode range. (Xilinx Answer 17505)
(SP1) 6.1i Architecture Wizard/Clocking Wizard - Changes to the clock buffer are not saved. (Xilinx Answer 17965)


(SP2) 6.1i/5.2i/5.1i COMPXLIB - When I compile for VCS, an error reports "[V2KS] Verilog 2000 IEEE 1364-2000 syntax used. Please compile with +v2k." (Xilinx Answer 17644)
(SP2) 6.1i COMPXLIB - "ERROR:cxl[env]:15- invalid MODELSIM env value detected." (Xilinx Answer 18233)

Constraints Editor

(SP2) 6.1i Constraints Editor - When I try to create an OFFSET IN constraint from the Advanced tab, no registered time groups appear in the Pad-to-Setup window. (Xilinx Answer 18039)
(SP2) 6.1i Constraints Editor - Block RAMs are not listed under the RAMs category. (Xilinx Answer 18256)
(SP2) 6.1i Constraints Editor - OFFSET OUT BEFORE and OFFSET IN AFTER are corrupted when saved. (Xilinx Answer 18257)
(SP2) 6.1i Constraints Editor - Port names for module port timing are corrupted. (Xilinx Answer 18258)
(SP2) 6.1i Constraints Editor - A FROM:TO PRIORITY constraint is corrupted. (Xilinx Answer 18259)
(SP1) 6.1i Constraints Editor - A PRIORITY on a PERIOD constraint is removed when I save. (Xilinx Answer 17936)

CORE Generator

(SP3) 6.1i COREGen - When called up from Project Navigator, COREGen reports "ERROR: Failure to create .sym symbol file. executable asy2sym is not in $XILINX." (Xilinx Answer 18290)


(SP2) 6.1i CPLD - Opening the HTML report causes Project Navigator to crash on Korean and Chinese operating systems. (Xilinx Answer 17713)
(SP1) 6.1i CPLD CoolRunner-II - An internally generated global clock does not function on the device. (Xilinx Answer 17909)
(SP1) 6.1i CPLD TAEngine - Timing constraints do not obey the proper FROM:TO location ranges. (Xilinx Answer 16742)


(SP1) 5.2i Data2BRAM - When I use BitGen with the -bd switch, the block RAM is initialized incorrectly. (Xilinx Answer 17387)
(SP1) 5.1i Data2BRAM - The DONE pin does not go High when the CRC check is disabled. (Xilinx Answer 15937)


(SP1) 6.1i Data2MEM - 47 - "WARNING: Not all BitLanes in ADDRESS_BLOCK "bram1" have BMM location constraints." (Xilinx Answer 17774)
(SP1) 6.1i Data2MEM - The "-log" command generates an empty log file. (Xilinx Answer 18010)


(SP1) 6.1i ECS - A Verilog keyword is misspelled as "inital" in a test fixture generated by SCH2Verilog. (Xilinx Answer 17955)


(SP3) 6.1i Floorplanner - The UCF written out by Floorplanner contains elements in an AREA GROUP that do not exist. (Xilinx Answer 18402)
(SP3) 6.1i Floorplanner - After PAR Floorplanner shows the logic, it does not display the I/O pins to which it connects. (Xilinx Answer 18403)
(SP3) 6.1i Floorplanner - FloorPlanner crashes when I try to exit (PC). (Xilinx Answer 18483)

HDL Bencher

(SP1) 6.1i HDL Bencher - HDL Bencher does not allow writing of pattens for an input bus. (Xilinx Answer 17956)
(SP1) 6.1i HDL Bencher - When I run a process dependent upon a TBW file, I am prompted to save the ".tbw" file even though no changes have been made. (Xilinx Answer 17957)
(SP1) 6.1i ISE - The "Generate Expected Simulation Results" process does not bring up a new HDL Bencher waveform. (Xilinx Answer 17958)


(SP2) 6.1i IBISWriter - The use of bidirectional pins causes IBISWriter to fail, reporting "ERROR:PostProcessors:38" (Virtex-II Pro). (Xilinx Answer 18254)


(SP3) 6.1i iMPACT - System ACE MPM/SC fails to erase/program Virtex/E. (Xilinx Answer 18550)
(SP3) 6.1i iMPACT - Spartan-3 devices always fail the verify process, even though the devices function correctly. (Xilinx Answer 18548)
(SP2) 6.1i iMPACT - "Erase/Program" for an XSVF File appears to complete, but the XCF (Platform Flash) PROMs are not operational. ("Verify" in BSCAN mode fails). (Xilinx Answer 18038)
(SP2) 6.1i iMPACT - Configuring a device chain containing more than three PROMs leads to: "ERROR:iMPACT:1624 - '1':Operation terminated". (Xilinx Answer 17820)
(SP2) 6.1i iMPACT - Programming an XC9500 with iMPACT takes twice as long as when JTAG Programmer is used. (Xilinx Answer 18153)
(SP1) 5.2isp3 iMPACT - Configuring larger Virtex-II Pro devices results in iMPACT recognizing XC2VP50 as XC2VP70, a verify failure, or other errors. (Xilinx Answer 13069)
(SP1) 6.1i iMPACT - "ERROR:iMPACT:1525 - File <path/design.bit> can not be found" is reported when I unarchive a System ACE project (Solaris) (Xilinx Answer 17511)
(SP1) 6.1i iMPACT - PROM File Generation Mode: When I add additional PROMs, the percentage utilized is not updated. (Xilinx Answer 17512)
(SP1) 6.1i iMPACT - A new ".bit" file is not loaded when I assign a new bitstream to a Virtex-II Pro device. (Xilinx Answer 17513)
(SP1) 6.1i iMPACT - When I program an XBR (CoolRunner-II) with OTF enabled, "ERROR:iMPACT - '1': Done bit could not be programmed correctly" is reported. (Xilinx Answer 17523)
(SP1) 5.2i iMPACT CPLD CoolRunner-II - The Global Set/Reset (GSR) pin does not function properly on an XC2C384 device. (Xilinx Answer 17545)
(SP1) 6.1i iMPACT - iMPACT hangs when I program in Slave Serial or SelectMap modes (Linux). (Xilinx Answer 17655)
(SP1) 6.1i iMPACT - Programming, erasing, or verifying CPLD with 1532 JEDEC file leads to iMPACT errors. (Xilinx Answer 18013)
(SP1) 6.1i iMPACT - Loading design files from a read-only directory causes iMPACT to crash. (Xilinx Answer 18015)
(SP1) 6.1i iMPACT - When I program a Virtex-II/II Pro device with an XSVF file, the DONE pin does not go High, even if iMPACT reports that programming is successful. (Xilinx Answer 18018)
(SP1) 5.2i iMPACT - Enabling "Automatic Checksum Insertion (CPLD & PROM)" results in "ERROR:iMPACT:1023 - 1... and USERCODE, ERASE, or Verify options greyed out". (Xilinx Answer 18019)
(SP1) 6.1i iMPACT - Configuring XC18V00 PROMs with a MultiLINX cable causes iMPACT Error 583. (Xilinx Answer 18022)
(SP1) 6.1i iMPACT - Using concurrent XSVF execution to erase, program, and verify an XC18V512 device results in an iMAPCT programming failure. (Xilinx Answer 18023)
(SP1) 6.1i iMPACT - Generating PROM files for QRVirtex (QRVR) devices results in "ERROR:iMPACT:131/882". (Xilinx Answer 18026)
(SP1) 6.1i iMPACT - Programming an XC2C64 device fails; iMPACT indicates that the device is in read-protect mode. (Xilinx Answer 18027)


(SP2) 6.1i Install - A message reports "Xilinx Service Pack 6.1.01i Setup cannot be installed over Xilinx install versions older than 6.1i", but no older ISE version is present. (Xilinx Answer 18151)


(SP3) 6.1i Virtex-II MAP - Use of the -timing switch leads to a PAR error. (Xilinx Answer 18264)
(SP3) 6.1i Virtex-II MAP - "FATAL_ERROR:Pack:pksvrbaseslice.c:249:1.16". (Xilinx Answer 18317)
(SP3) 6.1i MAP - "EXCEPTION:Xdm:FileReader.c..." error occurred on Aurora 201". (Xilinx Answer 18513)
(SP2) 6.1i MAP/PAR - A number of directed routing constraints are dropped when a design using KEEP_HIERARCHY constraints is mapped. (Xilinx Answer 17176)
(SP2) 6.1i Virtex-II MAP - An EDK ML300 Reference Design crashes in MAP (Windows). (Xilinx Answer 18029)
(SP2) 6.1i Spartan-IIE MAP - CLK2X180 net and loads are incorrectly trimmed. (Xilinx Answer 18088)
(SP2) 6.1i SP1 MAP - A MAP change (made in 6.1i SP1) to improve the handling of split carry chains may cause pack errors. (Xilinx Answer 18160)
(SP2) 6.1i Virtex-II MAP - A crash occurs when MAP is run with the "-timing" switch used. (Xilinx Answer 18230)
(SP2) 6.1i Virtex-II Pro MAP - "FATAL_ERROR: MapLib:basmmngm.c: 2232:1.154 - Physical signal abc of net..." (Xilinx Answer 18231)
(SP2) 6.1i SP1 Virtex-II MAP - MAP crashes during directed packing for a design containing LOC'd RAM32X1D components. (Xilinx Answer 18246)
(SP1) 6.1i Virtex-II MAP - Timing tools may flag a false path through F5MUX (Xilinx Answer 14864)
(SP1) 6.1i Virtex-II MAP - "ERROR:Pack:679 - Unable to obey design constraints..." (Xilinx Answer 16416)
(SP1) 6.1 Virtex/Virtex-II MAP/PAR - Designs with split carry chains might result in unroutable connections (Xilinx Answer 17179)
(SP1) 6.1i Virtex-II Pro MAP - "INTERNAL_ERROR:Place:baspltctask.c:261:1.36 - Error: '3'." (Xilinx Answer 17842)
(SP1) 6.1i Spartan-IIE MAP - MAP fails to handle a MULTAND circuit. (Xilinx Answer 17843)
(SP1) 6.1i Virtex-II MAP - BEL constraints on DPRAM symbols do not work. (Xilinx Answer 17844)
(SP1) 6.1i MAP - A core dump occurs when the -convert option is used on a design with no Area Groups. (Xilinx Answer 17845)

Modular Design

(SP2) 6.1i Modular Design - The sequential Modular Design flow does not work in the 6.1i software. (Xilinx Answer 17902)


(SP3) 6.1isp2: NGDBuild - "EXCEPTION:Xdm:xdm_stubread.c..." error occurred on Linux and Solaris and Segmentation Fault. (Xilinx Answer 18514)
(SP1) 6.1 NGDBuild - "ERROR:NGDBuild:604 - Logical Block ... in CPLD/CR." (Xilinx Answer 17937)
(SP1) 6.1 NGDBuild Spartan-3 - Use of the RSDS_25 standard leads to warning messages. (Xilinx Answer 17938)


(SP3) 6.1i PACE - PACE crashes upon opening when the LFP file is present. (Xilinx Answer 18515)
(SP2) 6.1i PACE - The PAR pad file does not match the CSV Import/Export headers. (Xilinx Answer 18260)
(SP1) 6.1i PACE - AREA GROUPs from my UCF do not appear in PACE when I attempt to assign a RANGE to them. (Xilinx Answer 17792)
(SP1) 6.1i PACE CPLD - I cannot create new designs for CPLDs. (Xilinx Answer 17940)
(SP1) 6.1i PACE - Edge constraints are not seen as valid LOC constraints. (Xilinx Answer 17941)
(SP1) 6.1i PACE CPLD - DRC errors occur on a UCF written by Lock Pins (Pin2UCF). (Xilinx Answer 17942)
(SP1) 6.1i PACE - Incorrect bus delimiters are written out in the UCF. (Xilinx Answer 17943)
(SP1) 6.1i PACE - Unrecognized constraints are deleted. (Xilinx Answer 17944)


(SP3) 5.1i PAR - Pad report are missing information on Iiternal pull-ups and voltages for VCINT, VCCO and VCCAUX. (Xilinx Answer 16099)
(SP3) 6.1i Virtex-II PAR - A crash occurs during Initial Timing Analysis on designs with partially constrained TBUF sets. (Xilinx Answer 18269)
(SP3) 6.1i Spartan-IIE PAR - The router cannot route all BLKRAM CLK loads with a low skew resource. (Xilinx Answer 18591)
(SP3) 6.1i Spartan-3 PAR - PAR crashes during Phase 7.18. (Xilinx Answer 18592)
(SP2) 6.1i Virtex-II Pro MAP - Virtex-II Pro designs containing GTI and GTO pads have long run times. (Xilinx Answer 18249)
(SP2) 6.1i SP1 Virtex-II PAR - The placer crashes in Phase 1.1 while placing a design containing LVDS I/O. (Xilinx Answer 18250)
(SP2) 6.1i Virtex-II PAR - Clock placer run time has improved in 6.1i SP2. (Xilinx Answer 18251)
(SP2) 6.1i Virtex-II PAR - A memory leak exists in the clock placer. (Xilinx Answer 18252)
(SP1) 6.1i Virtex-E PAR - Auto-hold time checking feature for Virtex/-E and Spartan-II/-E devices. (Xilinx Answer 17469)
(SP1) 6.1i Virtex-II PAR - A design with a locked multiplier and 512X36 BLKRAM hangs in Phase 5 of the router. (Xilinx Answer 17838)
(SP1) 6.1i Virtex-II PAR - Incorrectly constrained LUT RAM can lead to unroutable nets and long router run times. (Xilinx Answer 17839)
(SP1) 6.1i Spartan-3 PAR - Clock Placement does not take into account all SelectIO constraints. (Xilinx Answer 17840)
(SP1) 6.1i PAR - The Turns engine is broken in the 6.1i software. (Xilinx Answer 17841)

Partial Reconfiguration

(SP2) 6.1i Partial Reconfiguration - PAR fails after Phase 1.1 when bus macros are used in partial reconfiguration. (Xilinx Answer 17759)

Project Navigator

(SP3) 6.1i ISE - The ISE GUI takes a long time to update implementation options. (Xilinx Answer 18276)
(SP3) 6.1i ISE - Generating the VHDL testbench template causes "Error creating <design>_tb.vhd. Defaulting to boilerplate test bench. " (Xilinx Answer 18465)
(SP3) 6.1i ISE - The Core template not updated when cores are regenerated. (Xilinx Answer 18466)
(SP3) 6.1i ISE - Leonardo synthesis reports "Error: Could not find wire table: xcv2p-p20-5_avg". (Xilinx Answer 18467)
(SP2) 6.1i ISE - CPLD flows do not pass the WYSIWYG switch to CPLDFit. (Xilinx Answer 15847)
(SP2) 6.1i ISE - Synthesis fails, reporting "ERROR:HDLParsers:3014 - <VHDL File> Line xxx. Library unit <package name> is not available in library work." (Xilinx Answer 18183)
(SP2) 6.1i ISE - The generation of a simulation model fails, and an error reports "Can't read "p_SimModelRetainHierarchy": no such variable". (Xilinx Answer 18185)
(SP1) 6.1i ISE - In Project Navigator, Readback options are not available for Spartan-3 projects. (Xilinx Answer 17490)
(SP1) 6.1i ISE, Architecture Wizard - Any XAW file created with the 5.1i/5.2i Architecture Wizard must be recreated to be used in the 6.1i tools. (Xilinx Answer 17669)
(SP1) 6.1i ISE - Project Navigator/Synplicity: "@E:"<directory>\<source>.v":nn:n:nn:nn|Reference to undefined module <unisimcomponent name>". (Xilinx Answer 17679)
(SP1) 6.1i ISE - MPPR reports the following error if the Extra Effort property is disabled: "Can't read "mpprExtraEffortLevel": no such variable." (Xilinx Answer 17683)
(SP1) 6.1i ISE - Immediately after the Implement Design process runs, the process status mark is set to "?", indicating that the process is out of date. (Xilinx Answer 17953)
(SP1) 6.1i ISE - Created/Added StateCAD source is not retained in the project upon re-opening. (Xilinx Answer 17959)
(SP1) 6.1i ISE - Closing Project Navigator produces a runtime error. (Xilinx Answer 17960)
(SP1) 6.1i ISE - When I create multiple new projects with the Project Navigator New Project Wizard, sources for the first project are added to subsequent projects. (Xilinx Answer 17961)
(SP1) 6.1i ISE - An undocked (ripped) ISE Text Editor window indicates that the source is being modified outside of the editor. (Xilinx Answer 17963)
(SP1) 6.1i ISE - Project Navigator issues a "coregen_lock file found" error message when I create a new project. (Xilinx Answer 17964)
(SP1) 6.1i ISE - Project Navigator crashes after running Simulate Post-Fit VHDL Model with "Fatal Error:GUIUtilities:WinApp c:657 $Revision". (Xilinx Answer 17967)
(SP1) 6.1i ISE - Architecture Wizard does not show selections when I change the project device. (Xilinx Answer 17968)
(SP1) 6.1i ISE - The "View HDL Instantiation Template" process fails for a DCM component, reporting "vhdtdtfi:Declaration (Module <dcm_name>) not found." (Xilinx Answer 17971)
(SP1) 6.1i ISE - A ModelSim vlog command from ".fdo" file fails, reporting "Error: (vlog-7) Failed to open design unit file." (Xilinx Answer 17972)
(SP1) 6.1i ISE - The CPLD Fitter report is not available through Project Navigator if the design fails to fit. (Xilinx Answer 17973)
(SP1) 6.1i ISE - Closing Timing Analyzer produces an error message in the Project Navigator Console window: "can't read "_processlabel": no such variable." (Xilinx Answer 17974)
(SP1) 6.1i ISE - Migrating a project from version 5.2i or earlier to 6.1i causes: "ERROR:Guide:251 - The design guide file, <project directory name>\guide.ncd, is already in the ISE 6.Xi format, no conversion necessary." (Xilinx Answer 17975)


(SP3) 6.1i PROMGen - Support for a platform Flash PROM revisioning CFI file .(Xilinx Answer 17606)


(SP2) Spartan-3 - Does Spartan-3 support the LVPECL I/O standard? (Xilinx Answer 18070)
(SP2) Spartan-3 - Can I put RSDS_25 I/Os in the same bank as LVDS_25, LVDS_EXT_25, and LDT_25? (Xilinx Answer 18152)

Speed Files

(SP3) 6.1i Speed Files - Virtex-II Pro, version 1.83 in Service Pack 3. (Xilinx Answer 18516)
(SP2) 6.1i Speed Files - A Spartan-3 Tiopid is too large in PREVIEW 1.22 for "-4". (Xilinx Answer 18261)
(SP1) 6.1i Speed Files - What changed in the Virtex-II Pro version 1.81 speed files, and how can I access these files? (Xilinx Answer 17719)
(SP1) 6.1i Timing/Speed Files - Package flight time is included in the speed files. (Xilinx Answer 17945)


(SP3) 6.1i Timing Analyzer/TRCE - Why aren't the specified number of unconstrained paths reported? (Xilinx Answer 18503)
(SP3) 6.1i Timing Analyzer - Why do some links for delay definitions point to a page stating "Topic not found"? (Xilinx Answer 18504)
(SP3) 6.1is1 Timing Analyzer - The Unconstrained Path Report contains errors, but paths are listed. (Xilinx Answer 18518)
(SP3) 6.1is2 Timing/PAR - PAR failed, reporting "WARNING:Timing:2666 - Constraint ignored..." (Xilinx Answer 18519)
(SP3) 6.1i Timing Analyzer - Timing Analyzer crashes when I change the speed grade without exiting. (Xilinx Answer 18520)
(SP2) 6.1i Timing Analyzer - A setup violation is reported on all Virtex-II Pro PowerPC Core reset pins. (Xilinx Answer 17584)
(SP2) 6.1i Timing Analyzer/TRCE - In a hold analysis, clock phase information is not used in an OFFSET IN constraint without the VALID keyword. (Xilinx Answer 17864)
(SP2) 6.1i Timing Analyzer - The character limit in the "Find What" box is not large enough. (Xilinx Answer 18262)
(SP1) 6.1i Timing Analyzer - How do I create a constraint for clock-forwarding that goes FROM my input clock pad THRU the FF clock pin TO my DDR output clock pad? (Xilinx Answer 17604)
(SP1) 6.1i Timing Analyzer - Filter paths in the Report Browser cannot be changed after the initial setting. (Xilinx Answer 17939)
(SP1) 6.1i Timing Analyzer/TRCE - The FROM:TO constraint no longer performs a hold check. (Xilinx Answer 17946)
(SP1) 6.1i Timing Analyzer - The tool crashes if I select reg_sr_q (PTC) or Report Fastest Paths. (Xilinx Answer 17947)
(SP1) 6.1i Timing Analyzer/TRCE - Positive non-zero hold times are reported for Virtex-E devices in the "data sheet" section. (Xilinx Answer 17948)


(SP3) 6.1i Virtex-II/Pro, Package Files - RSVD pins are now listed as NC (No Connect). (Xilinx Answer 18578)


(SP3) 6.1i XPower - Supported devices are XPLA3, CoolRunner-II, Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, and Virtex-II Pro. (Xilinx Answer 12091)
(SP2) 6.1i XPower - Repeatedly running "Estimate Activity Rates" causes power to increase for CPLD designs. (Xilinx Answer 17790)
(SP1) 6.1i XPower CPLD - The Summary tab current/power values incorrectly initialize to "0" when the design is first loaded. (Xilinx Answer 17593)
(SP1) 6.1i XPower - Running Estimate Activity Rates more than once causes power to increase. (Xilinx Answer 17910)
(SP1) 6.1i XPower - The sum of the individual power requirements does not equal the total power required. (Xilinx Answer 17911)
(SP1) 6.1i XPower - Attempting to save my settings causes the program to crash (Linux). (Xilinx Answer 17912)


(SP3) 6.1i XST - XST generates incorrect logic for a counter design. (Xilinx Answer 18123)
(SP2) 6.1i XST - "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13." (Xilinx Answer 17481)
(SP1) 6.1i XST - Known Issues for the mixed language flow. (Xilinx Answer 16241)
(SP1) 6.1i XST - "INFO:Xst:1799 - State 10000000000 is never reached in FSM <STATE>." (Xilinx Answer 16256)
(SP1) 6.1i XST - "WARNING:Xst:1887 - Unable to fit FSM <FSM_0> in BRAM." (Xilinx Answer 16904)
(SP1) 6.1i XST - "WARNING:NgdBuild:483 - Attribute 'INIT' on 'signal_name' is on the wrong object." (Xilinx Answer 17275)
(SP1) 6.1i XST - "Warning: The following connections close logic loops, and some paths through these connections may not be analyzed," (Xilinx Answer 17527)
AR# 18011
Date Created 09/11/2003
Last Updated 04/27/2006
Status Archive
Type General Article