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AR# 18031

LogiCORE 10 Gigabit Ethernet MAC XAUI v3.0 - Incorrect MDC clock crossing prevents MDIO interface from working


Keywords: 10, Ten, Gigabit, Ethernet, MAC, XGMAC, V3.0, XAUI, MDC, clock, MDIO, Metastability

Urgency: Standard

General Description:
The XAUI core contains a management block where P_MDC_RISING is used to detect a rising edge on MDC. MDC is asynchronous to CLK. The circuit can fail to detect the rising edge if MDC transitions near CLK edge (thus violating the setup/hold requirements) preventing the MDIO interface from working.


A Metastable condition can occur if the P_MDC_RISING signal transitions about the CLK edge. For more information on Metastability in Xilinx devices, please see (Xilinx XAPP094).

In order for the edge detection circuit to work correctly, it needs to see a '1' on MDC and a '0' on MDC_LAST. If a metastable condition occurs on P_MDC_RISING, it can cause the MSC_LAST register to be either '0' or '1'. A '0' will cause this issue.

Double registering solves the problem because it synchronizes MDC to CLK prior to the edge detection circuit. Thus, MDC_LAST will no longer go metastable and the circuit is predictable. Hence for V3.0 of this core, an external flip-flop must be added onto MDC.

This is not an issue with v4.0 of the core.
AR# 18031
Date Created 09/15/2003
Last Updated 08/31/2006
Status Archive
Type General Article