UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18048

3.2 / 6.1 EDK - The PPC405 DSOCM and ISOCM DCR base address registers are assigned to zero

Description

Keywords: DCR, OCM, TIEDSOCMDCRADDR, TIEISOCMDCRADDR, PPC, XPS, Addresses

Urgency: Hot

General Description:
The PPC405 DCR base address control registers for the DSOCM (TIEDSOCMDCRADDR) and ISOCM (TIEISOCMDCRADDR) are set to zero when they are not assigned in the MHS file. This results in the DCR addresses overlapping. This is a problem only when the DCR bus is used.

Solution

Verify that the following parameters have been specified for each controller:

BEGIN isbram_if_cntlr
PARAMETER INSTANCE = isbram_if_cntlr1
PARAMETER HW_VER = 1.00.a
PARAMETER C_TIEISOCMDCRADDR = 0x06

BEGIN dsbram_if_cntlr
PARAMETER INSTANCE = dsbram_if_cntlr1
PARAMETER HW_VER = 1.00.a
PARAMETER C_TIEDSOCMDCRADDR = 0x07

AR# 18048
Date Created 09/16/2003
Last Updated 03/07/2006
Status Archive
Type General Article