For high-speed applications, it has been standard design practice to use Flip-Chip packages over wire-bonded ones. The I/O trace lengths in the substrate affect performance, especially in high-speed applications. This stems from the current path between the die and the substrate balls. The electrical delay of the Flip-Chip substrate traces are much easier to predict than those of wire-bonded package wires. In high-speed design applications, these delays could be quite significant, and there is a need to include these in performance analysis models. Please refer to
(Xilinx Answer 15321) on how to acquire these details for a specific device package combination.
The Flip-Chip packages have a structural arrangement that make delays associated with these traces very predictable within reasonable tolerance. Wire-bond packages do not have a convenient arrangement that lends to this sort of predictable "flight time" within reasonable tolerance. Xilinx wire-bonded BGA packages (BG, CS and FG) have a combination of traces in substrates and bond wires. Although the delays associated with the package trace lengths can be well-modeled and predicted at about 6.0 - 7.1ps/mm, the delays associated with the bond-wires are not consistent and not easy to model with precision. Since flight-time-sensitive designs are usually not implemented in wire-bonded packages and since these package structures do not lend themselves to this kind of analysis, Xilinx does not have this information available.