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AR# 18093

6.1i CORE Generator - Design with CORE Generator modules fails synthesis "ERROR:HDLParsers:3312....Undefined symbol 'xxx'."


A schematic or HDL design containing CORE Generator modules might fail during synthesis with an error similar to the following:

"ERROR:HDLParsers:3312 - D:/cases/..../sig.vhd Line 207. Undefined symbol 'C_ADDSUB_V6_0'. Undefined symbol 'LUT4'."

XST is starting to synthesis the behavioral VHDL file, hence the complaint. If the XCO file is removed from the project, then the synthesis goes through with no problems.


This problem can be caused by a specific set of Xilinx Cores which have a syntax error in the wrapper file ("<core_name>.vhd").

The "<core_name>.vhd" file contains component instantiations that are only for synthesis and should be surrounded by the translate on/off statements. However, the translate on/off statements were misplaced and only surround the library definitions.

To work around this issue, place translate on/off around the entire source (from just after BEGIN in the architecture, to just above "end xilinx"). This prevents XST from synthesizing these simulation instantiations and allows XST to complete.

This problem has been fixed in the 6.1i CORE Generator IP update #1 (G_IP1).
AR# 18093
Date Created 09/03/2007
Last Updated 02/17/2011
Status Archive
Type Error Message