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AR# 18095

Spartan-3/-3E - Can I interface a 3.3V LVDS or LVPECL device to a Spartan-3/-3E?

Description

Spartan-3/-3E supports only LVDS_25 and LVPECL_25. Can I interface a 3.3 volt LVDS or LVPECL device to Spartan-3/-3E FPGAs?

Solution

LVDS_33 and LVPECL_33 I/O buffers are not available for instantiation because Spartan-3/-3E devices support only LVDS_25 and LVPECL_25 (Spartan-3E supports only LVPECL_25 inputs, but not outputs). You can interface an LVDS_33 or LVPECL_33 signal to a LVDS_25 and LVPECL_25 input on a Spartan-3/-3E because the input specifications for LVDS_25/33 and LVPECL_25/33 are identical.

Differential Input Buffers are powered by VCCAUX and are not VCCO-dependent. Consequently, you can put LVDS_25 and LVPECL_25 input buffers in a 3.3V bank without damaging the device. Instantiating a LVDS_25 or LVPECL_25 input buffer in 3.3V bank does not generate a software error.

NOTE: If you are using DIFF_TERM in Spartan-3E, the bank voltage must be set to 2.5V as the internal termination network is biased to expect 2.5V on VCCO. Spartan-3E input-only differential pins do not support DIFF_TERM. If you are using external differential termination, LVDS_25 and LVPECL_25 inputs can be placed in either 2.5V or 3.3V banks. For more information on DIFF_TERM, see (Xilinx Answer 19627).

For Spartan-3A/-3AN/-3A DSP devices, you can use DIFF_TERM in either a 2.5 or 3.3V bank. A 3.3V bank is actually preferred because the DIFF_TERM resistor is calibrated more accurately. See the device data sheet for values.

Differential Output Buffers for Spartan-3/-3E MUST be put in a 2.5V bank because they were not designed to operate from either 3.3 or 2.5v VCCO, but only from a 2.5v VCCO (and still meet the LVDS IO specification). Instantiating a LVDS_25 or LVPECL_25 output buffer in 3.3V bank will generate a software error.

LVDS_25_DCI differential input and output buffers must be placed in a 2.5V bank because the reference resistors and DCI termination resistors are biased to expect 2.5V on VCCO.

For more information on interfacing the LVPECL 3.3V driver with Xilinx 2.5V differential receivers, see (Xilinx XAPP696): "Interfacing LVPECL 3.3V Drivers With Xilinx 2.5V Differential Receivers."

LVDS and LVPECL specifications and resistor termination information are available in the FPGA DC and Switching Characteristics section of the data sheet.

The Spartan-3 FPGA DC and Switching Characteristics Data Sheet is located at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
FPGA Device Families -> Spartan-3/3L -> "Spartan-3 FPGA DC and Switching Characteristics"

The Spartan-3E FPGA DC and Switching Characteristics Data Sheet is located at:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp
FPGA Device Families -> Spartan-3E -> "Spartan-3E FPGA DC and Switching Characteristics"

AR# 18095
Date Created 09/03/2007
Last Updated 02/28/2013
Status Active
Type General Article
Devices
  • Spartan-3
  • Spartan-3E