UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18099

3.1 SP1 System Generator for DSP - Why is my RAM or ROM block larger than expected when I generate the core or use the Resource Estimator?

Description

General Description: 

When the depth of SPRAM, SPROM relates to the input address width (a_w) in the following way: 2^(a_w-1)<depth<2^(a_w), the SysGen SPRAM and SPROM block should generate the core using the depth value I entered. This change would reduce the numbers of Block RAM primitives needed by the design. 

 

Also, the Resource Estimator for Single-Port Block RAM and ROM should use the depth value specified in the GUI instead of deriving it from the address width. However, this is not happening.

Solution

This has been fixed in System Generator 3.1 Service Pack 1, available at: 

http://www.xilinx.com/products/software/sysgen/sg_intro.htm

AR# 18099
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article