We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18114

3.1 SP1 System Generator for DSP - Why does Hardware Co-Sim generate mismatch errors when using a long simulation interval?


General Description: 

The SysGen v3.1 co-simulation S-function relies on Simulink to keep track of the simulation time. The S-function uses this time to determine how many times the system clock should be stepped during a simulation cycle. If the variable-step solver is used, Simulink eventually looses accuracy in the time it reports, and the time interval continuously gets smaller and smaller. Because of this discrepancy, the Co-Sim S-function will eventually step the clock an incorrect number of cycles, and users will see simulation mismatches as a result.  


NOTE: This behavior is not seen if fixed-step solver is used.


This has been fixed in System Generator 3.1 service pack 1 



AR# 18114
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article