AR #18115 - 8.1i/7.1i Simulation - DCM outputs are "0" and the DCM does not lock (UniSim and SimPrim VHDL models) (DCM reset requirement)
8.1i/7.1i Simulation - DCM outputs are "0" and the DCM does not lock (UniSim and SimPrim VHDL models) (DCM reset requirement)
| AR# | 18115 |
| Part | SW-Sim Libraries |
| Last Modified | 2008-11-19 00:00:00.0 |
| Status | Archive |
| Keywords | 61, SP1, Service Pack 1, broken, RST |
Description
Keywords: 61, SP1, Service Pack 1, broken, RST
When I run a DCM simulation in 6.1i, the outputs are "0" and the DCM does not lock. This simulation was working in the 5.1i/5.2i versions of the ISE design tools.
Solution
New requirements have been introduced into the DCM model that are causing this discrepancy. These requirements have been added based on new results from testing the DCM. The new requirements are as follows:- The RST input signal is asynchronous and should be held High for at least three clock cycles.
- While the DCM is in reset, a valid clock should be provided to the CLKIN pin of the DCM.
The older DCM model was not checking for this condition.
The Virtex-II/-II Pro and Spartan-3 User Guides list these requirements as well:
http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Beginning with the ISE 8.1i Service Pack 2, if these requirements are not met, the LOCK signal will go to X.