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AR# 18122

3.1 SP1 System Generator for DSP - Release Notes / README


General Description: 

This README contains the Release Notes for the 3.1 Service Pack 1 System Generator for DSP. The Release Notes include a list of the issues that are fixed by this Service Pack.


Why is my RAM or ROM block larger than expected when generating the core or using the resource estimator? (Xilinx Answer 18099)


Why does the resource estimator fail on addsub block when "pipeline" option is selected? (Xilinx Answer 18100)


Why does a space in the extended block name cause an error? (Xilinx Answer 18101)


Why does the MCode block only allow binary point to be less than the bit width and not equal to the bit width? (Xilinx Answer 18102)


Why does Hardware Co-Simulation fail to create a Co-Sim run-time library if name is > 63 characters? (Xilinx Answer 18103)


Why does the run-time Hardware Co-Sim block have a limited number of ports? (Xilinx Answer 18104)


Why doesn't Hardware Co-Sim provide an error message if a library with the same name already exists? (Xilinx Answer 18105)


Why can't SysGen generate block memory for Spartan-3 devices? (Xilinx Answer 18108)


Why can't SysGen use the dedicated multipliers for Spartan-3 devices? (Xilinx Answer 18109)


Why does the Resource Estimator report the wrong memory size for Spartan-3 devices? (Xilinx Answer 18110)


Why does SysGen error when using some from/goto combinations? (Xilinx Answer 18111)


Why does Hardware Co-Sim generate mismatch errors when using a long simulation interval? (Xilinx Answer 18114)


Why does SysGen 3.1 give a fatal error when a subsystem contains the disregard block? (Xilinx Answer 18121)


Why are the constant values sometimes incorrect when SysGen generates the VHDL for an MCode block? (Xilinx Answer 17627)


What are the known issues for System Generator v3.1 SP1? (Xilinx Answer 17773).

AR# 18122
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article