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AR# 18123

6.3i/6.2i/6.1i XST - XST generates incorrect logic for a counter design

Description

Keywords: if, elsif, else, set, reset, behavioral, post-translate, netlist, clear, synchronous

When a counter is controlled by a combination of synchronous clear, set, constant load and count enable in the same process, the behavioral simulation is different from the post-translate simulation indicating that XST produced incorrect logic during synthesis.

Solution

This problem has been fixed in ISE 7.1i.

To work around this issue, put the control signals in one process and the counter in another process. The code below represents VHDL code that XST will synthesize incorrectly:

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity compile_test is
Port ( clk : in std_logic; -- System clock
lock : in std_logic; -- Set lockout flag
lock3 : in std_logic; -- Lockout for 2 cycle
lock4 : in std_logic; -- Lockout for 3 cycles
lock10 : in std_logic; -- Lockout for 9 cycles
lockout : out std_logic
);
end compile_test;

architecture behavioral of compile_test is

signal locktim : unsigned(2 downto 0) := "000"; -- Init values just for simulation
signal locked : std_logic := '0';

begin

process (clk)
begin
if clk'event and clk = '1' then
if lock = '1' then -- When lock is asserted
locked <= '1'; -- Set lockout flag
elsif locktim = 0 then -- When count expires
locked <= '0'; -- Release the lockout flag
end if;
end if;
end process;

lockout <= lock or locked;

process (clk)
begin
if clk'event and clk = '1' then
if lock = '1' then -- When lock asserted
if lock10 = '1' then -- And lock10 driven
locktim <= "111"; -- Load counter with 7
elsif lock3 = '1' then -- Else if lock3 driven
locktim <= "000"; -- Load the counter with 0
elsif lock4 = '1' then -- Else if lock 4 driven
locktim <= "001"; -- Load the counter with 1
else
locktim <= "000"; -- Else load counter with 0
end if;
elsif locked = '1' then -- When lock removed and locked flag set
locktim <= locktim - 1; -- Start decrementing the counter
end if;
end if;
end process;


end behavioral;


Change the above code to the following:


LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity compile_test is
Port ( clk : in std_logic; -- System clock
lock : in std_logic; -- Set lockout flag
lock3 : in std_logic; -- Lockout for 2 cycle
lock4 : in std_logic; -- Lockout for 3 cycles
lock10 : in std_logic; -- Lockout for 9 cycles
lockout : out std_logic
);
end compile_test;

architecture behavioral of compile_test is

signal locktim : unsigned(2 downto 0) := "000"; -- Init values just for simulation
signal locked : std_logic := '0';
signal tmp: unsigned(2 downto 0); -- XGR

begin

process (clk)
begin
if clk'event and clk = '1' then
if lock = '1' then -- When lock is asserted
locked <= '1'; -- Set lockout flag
elsif tmp = 0 then -- When count expires
-- elsif locktim = 0 then
locked <= '0'; -- Release the lockout flag
end if;
end if;
end process;

lockout <= lock or locked;

process (lock,lock10,lock3,lock4,tmp_xgr)
begin
if lock = '1' then -- When lock asserted
if lock10 = '1' then -- And lock10 driven
locktim <= "111"; -- Load counter with 7
elsif lock3 = '1' then -- Else if lock3 driven
locktim <= "000"; -- Load the counter with 0
elsif lock4 = '1' then -- Else if lock 4 driven
locktim <= "001"; -- Load the counter with 1
else
locktim <= "000"; -- Else load counter with 0
end if;
else -- When lock removed and locked flag set
locktim <= tmp; -- Start decrementing the counter
end if;
end process;

--Added process for control signal
process (clk)
begin
if clk'event and clk = '1' then
if (locked = '1' and lock = '0') then
tmp <= locktim - 1;
else
tmp <= locktim;
end if;
end if;
end process;

end behavioral;

AR# 18123
Date Created 09/03/2007
Last Updated 01/06/2009
Status Archive
Type General Article