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AR# 18156

LogiCORE RapidIO- A problem with 6.1i SimPrims X_LATCHE.v and X_LATCH.v models causes simulation of a RapidIO design to hang


General Description: 

During functional or timing simulation of the RapidIO LogiCORE in 6.1i, the simulation hangs during training.


This problem has been fixed in the latest Xilinx ISE service pack. Please download the service pack from the Xilinx Web site located at: 



The first service pack containing this fix was Service Pack 2.

AR# 18156
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article