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AR# 18167

LogiCORE SPI-4.2 (POS-PHY L4) v6.0 - Dynamic Phase Alignment Sink core does not go in-frame

Description

Keyword: Core, Generator, COREGen, SPI, PL4, DPA, snkoof, framing, timing, constraint, ts_align_req, rdclkdiv_gp, rdclk0_gp 

 

 

 

General Description 

The SPI-4.2 Sink core I am using in Dynamic configuration does not go in-frame.

Solution

This problem is due to a timing issue in the core. This issue was corrected in version 6.0.1 of the core (available as of October 13, 2003), in which the UCF file was corrected. 

 

If you are using SPI-4.2 v6.0: 

The following two constraints must be added to the "pl4_wrapper.ucf" file: 

 

 # Set the timing constraint between RDClkDiv_GP to RDClk0_GP clock domain: 

NET "pl4_snk_top0/RDClk0_GP" TNM_NET = "RDClk0_GP"; 

TIMESPEC TS_ALIGN_REQ = FROM : RDClkDiv_GP : TO : RDClk0_GP : TS_RDClk_P ; 

 

Because of the above change, the -4 phase shift in the following section should be commented out (or changed to 0): 

 ###################################################################### 

 # RDClk DCM Phase Shift 

 # Note: The instance name may require modification to reflect the user's design  

 # hierarchy and synthesis tools. 

 ###################################################################### 

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk_dcm0" CLKOUT_PHASE_SHIFT = FIXED; 

 

 # The PHASE_SHIFT value must not be altered: 

INST "pl4_snk_top0/pl4_snk_clk0/DynamicAlignV2.rdclk_dcm0" PHASE_SHIFT = -4; 

(comment this line out) 

 

 #EOF: $RCSfile: dyn_phase_ucf.align,v $

AR# 18167
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article