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AR# 18203

6.1i ECS - ModelSim Functional Simulation, VHDL - "ERROR: No actual specified for clkfb, clkin, dssen, psclk, psen, psincdec, psincdec, rst"

Description

Keywords: ISE, 6.1, ECS, schematic, vhf, DCM, actual, specified, functional, simulation, ModelSim, Modelsim, MTI

Urgency: Standard

General Description:
When I try to do a functional simulation of my schematic design, ModelSim fails with the following error:

"# -- Compiling entity design
# -- Compiling architecture behavioral of design
# ** Error: design.vhf(114): No actual specified for clkfb.
# ** Error:design.vhf((114): No actual specified for clkin.
# ** Error: design.vhf(114): No actual specified for dssen.
# ** Error: design.vhf(114): No actual specified for psclk.
# ** Error: design.vhf(114): No actual specified for psen.
# ** Error: design.vhf(114): No actual specified for psincdec.
# ** Error: design.vhf(114): No actual specified for rst.
# -- Loading package textio
# -- Loading package vital_primitives
# -- Loading package vpkg
# -- Loading entity dcm
# ** Error: design.vhf(116): near "port": expecting: END_
# ERROR: C:/Modeltech57c_xe/win32xoem/vcom failed.
# Error in macro ./design_test.fdo line 5
# C:/Modeltech57c_xe/win32xoem/vcom failed.
# while executing
# "vcom -93 -explicit top.vhf"

These error messages are related to the use of the DCM. How can I solve this problem?

Solution

This problem is due to a syntax error in the ".vhf" file generated by ECS (Schematic Editor). ECS adds a semicolon at the end of generic map statement in the DCM port mapping. This semicolon will also cause ModelSim to generate the following error message:

"Error: design.vhf( line_number): near "port": expecting: END"

To work around to this problem, delete the semicolon and rerun the simulation.

NOTE: If you are not using the STATUS output of the DCM, another problem might arise while compiling the Functional model of your design.

The following statement in the DCM port mapping will make ModelSim error out:
STATUS(7 downto 0)=> open

ModelSim will fail with the following error message:

"Error: design.vhf(line_number): Formal status must not be associated with OPEN when subelements are associated individually"

To solve this problem you can:

Change the compilation option for ModelSim to 87 instead of 93. A warning will be generated, but the simulation will go through.

or

Modify your schematic by adding a signal on the STATUS ouput of DCM.

NOTE: Leave this signal unconnected. Since this signal is not connected, it will be automatically optimized away during the Xilinx Flow.

For more details on the latter error message, please refer to (Xilinx Answer 15691).
AR# 18203
Date Created 10/08/2003
Last Updated 01/08/2006
Status Archive
Type General Article