UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18274

LogiCORE SPI-3 (POS-PHY L3) v2.0.1 - OFFSET constraints fail timing in ISE 6.1.01

Description

Urgency: Standard 

 

Problem Description: 

For a PL3 design, timing fails the OFFSET constraints on the PL3 signals when running with ISE 6.1.01 or earlier software.

Solution

Timing passes on all constraints when using service pack 2 of ISE 6.1. 

 

Phase shift constraints can be added to the DCM signals, Rx and Tx as follows: 

 

INST "TFClkDCM" CLKOUT_PHASE_SHIFT = FIXED; 

INST "TFClkDCM" PHASE_SHIFT = 40; 

INST "RFClkDCM" CLKOUT_PHASE_SHIFT = FIXED; 

INST "RFClkDCM" PHASE_SHIFT = 40; 

 

The actual phase shift values are system dependent and will likely need to be changed to reflect the user system.

AR# 18274
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article