UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18288

6.2 System Generator for DSP and LogiCORE DDS v4.1 - How do I specify the phase increment for the DDS v4.1 module?

Description


General Description:

How do I specify the phase increment for the DDS in System Generator for DSP v6.2?

Solution


The output frequency of the DDS is controlled by its phase increment. A phase increment of one tenth (1/10) for the DDS implies that in ten time samples, one sinusoid is completed.



If you use a register type phase increment, the DATA port of the DDS can be fed by a constant fraction with the format UFIX_32_32. Note that there is a restriction on the DATA input of the DDS port as follows:



- must be 32 bits (the DDS's accumulator width)

- must be unsigned

- binary point position must be equal to the binary width



There is a Xilinx Blockset Constant in the SysGen library; all constants must have a sample time explicitly defined.



NOTE: The phase increment is not specified in the same manner as is indicated by the linked CORE Generator DDS core data sheet in the help information for the DDS



The System Generator flow allows you to enter a fraction. For a definition of this fraction, double-click the DDS block and then click the Help button.
AR# 18288
Date Created 09/03/2007
Last Updated 12/17/2011
Status Archive
Type General Article