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AR# 18312

Virtex-II Pro "proc_sys_reset" - C_NUM_BUS_RST does not work as expected

Description

General Description: 

Documentation for the "proc_sys_reset" states that you should set C_NUM_BUS_RST to the number of busses in the system. So I set it to two, and it broke. I tried "sys_bus_reset(0)" and "sys_bus_reset(1)" for the PLB and OPB, and it didn't like that. How are you supposed to connect this, and is it really necessary?

Solution

The current MHS Syntax doesn't support this feature. However, it will be supported in EDK 6.2i. 

 

Option1:  

C_NUM_BUS_RST = 1 

 

This is the default, and no modification is needed. The reset out of the "proc_sys_reset" IP will have a 1-bit output assigned to all the resets within the system.

 

Option 2: 

C_NUM_BUS_RST = 2 

 

Here is an snippet from an MHS using the "util_bus_split" IP. 

 

BEGIN proc_sys_reset 

PARAMETER INSTANCE = reset_block 

PARAMETER HW_VER = 1.00.a 

PARAMETER C_EXT_RESET_HIGH = 0 

# Set C_NUM_BUS_RST to 2 

PARAMETER C_NUM_BUS_RST = 2  

PORT Slowest_sync_clk = sys_clk_s 

PORT Ext_Reset_In = sys_rst_s 

PORT Chip_Reset_Req = C405RSTCHIPRESETREQ 

PORT Core_Reset_Req = C405RSTCORERESETREQ 

PORT System_Reset_Req = C405RSTSYSRESETREQ 

PORT Rstc405resetchip = RSTC405RESETCHIP 

PORT Rstc405resetcore = RSTC405RESETCORE 

PORT Rstc405resetsys = RSTC405RESETSYS 

# The sys_bus_reset will be 2 bits 

PORT Bus_Struct_Reset = sys_bus_reset 

PORT Dcm_locked = clk_lock 

END 

 

BEGIN util_bus_split 

PARAMETER INSTANCE = util_bus_split_0 

PARAMETER HW_VER = 1.00.a 

# Size of input bus sys_bus_reset 

PARAMETER C_SIZE_IN = 2 

PARAMETER C_SPLIT = 1 

PARAMETER C_LEFT_POS = 1 

# Input bus is 2 bits 

PORT Sig = sys_bus_reset 

# Out1 and Out1 are 1 bit each 

PORT Out1 = plb_reset 

PORT Out2 = opb_reset 

END 

 

BEGIN plb_v34 

PARAMETER INSTANCE = plb 

PARAMETER HW_VER = 1.01.a 

PARAMETER C_DCR_INTFCE = 0 

PARAMETER C_EXT_RESET_HIGH = 1 

PORT PLB_Clk = sys_clk_s 

# 1 bit reset for plb coming from util_bus_split 

PORT SYS_Rst = plb_reset 

END 

 

BEGIN opb_v20 

PARAMETER INSTANCE = opb1 

PARAMETER HW_VER = 1.10.b 

PORT OPB_Clk = sys_clk_s 

# 1 bit reset for opb coming from util_bus_split 

PORT SYS_Rst = opb_reset 

END

 

Option 3: 

C_NUM_BUS_RST = 3 or greater 

 

In this case, a custom IP will need to be created. For this example, C_NUM_BUS_RST=3. In turn, this will produce a "sys_bus_reset" that is 3 bits wide. If a larger value is needed, then modify the vhdl code, MPD, and PAO files to reflect the added output ports. 

 

VHDL File 

 

library IEEE; 

use IEEE.std_logic_1164.all; 

 

entity my_bus_spliter is 

port ( 

-- input bus 

bus_in : in std_logic_vector(0 to 2); 

-- output bits, if larger than 3,  

-- then add then number of single bit outputs  

rst0 : out std_logic; 

rst1 : out std_logic; 

rst2 : out std_logic); 

end my_bus_spliter; 

 

architecture imp of my_bus_spliter is 

begin 

rst0 <= bus_in(0); 

rst1 <= bus_in(1); 

rst2 <= bus_in(2); 

end imp; 

 

MPD File 

 

BEGIN my_bus_spliter 

OPTION IP_GROUP = INFRASTRUCTURE 

OPTION IPTYPE = PERIPHERAL 

OPTION IMP_NETLIST = TRUE 

OPTION HDL = VHDL 

PORT bus_in = "", DIR=IN, VEC=[0:2] 

PORT rst0 = "", DIR=OUT 

PORT rst1 = "", DIR=OUT 

PORT rst2 = "", DIR=OUT 

END 

 

PAO File 

 

lib my_bus_spliter my_bus_spliter

AR# 18312
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article