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AR# 18325

6.1 EDK, SimGen - Sub-module simulation is not supported

Description

Keywords: SimGen, simgen, sub-module, simulation, EDK, edk

Urgency: Standard

General Description:
When simulating my sub-module design, SimGen errors out, stating that sub-module simulation is not supported.

Solution

To work around this problem, you can change the Design Hierarchy to toplevel design.

Currently, Behavioral simulation for Verilog is not supported. See (Xilinx Answer 15796).
AR# 18325
Date Created 10/29/2003
Last Updated 04/09/2007
Status Archive
Type General Article