UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 18338

LogiCORE SPI-3 (POS-PHY L3) - What is the difference between SPI-3 v2.0 and v3.x core?

Description

General Description 

Currently, there are several versions of SPI-3 (PL3) available on the SPI-3 lounge. What are the differences between these versions?

Solution

Differences between SPI-3 v2.x and v3.x SPI-3 v2.x and v3.x: 

 

FIFO Configuration: 

The SPI-3 v2.x core is supported for only 1, 2, and 4 channel configurations. These cores have embedded per-channel FIFOs, and therefore perform flow-control and channel arbitration automatically.  

 

The SPI-3 v3.x core supports between 1 - 256 channels, and contains a single FIFO. This configuration allows users to implement data storage and flow-control external to the core, such that it can be optimized for the application.  

 

Parity:  

The SPI-3 v2.x core only supports a real-time parity indication. There is no way to correlate the parity error to the data stored in the FIFO, because the parity bit is flagged as data is received across the SPI-3 interface. If per-packet parity indication is required, migration to the SPI-3 v3.x core is recommended.  

 

The SPI-3 v3.x core supports a parity indication associated with user data. There is a separate parity bit for address, and one for data. Both of these parity bits are passed through the FIFO along with the user data, such that the user can determine which packet caused the parity error. If this functionality is required, then it is recommended that you use the SPI-3.x core.  

 

For detailed information on the SPI-3 v2.x or v3.x cores, refer to the specific data sheets available on the SPI-3 IP Lounge.

AR# 18338
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article